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6-output clock generator with integrated 1.6 ghz vco ad9518-4 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. on .a. tel: om fax: ed. e technology way, p.o. box 9106, norwood, ma 02062-9106, u.s 781.329.4700 www.analog.c 781.461.3113 ?2007C2010 analog devices, inc. all rights reserv features low phase noise, phase-locked loop (pll) on-chip vco tunes from 1.45 ghz to 1.80 ghz external vco/vcxo to 2.4 ghz optional 1 differential or 2 single-ended reference inputs reference monitoring capability auto and manual reference switchover/holdover modes autorecover from holdover accepts lvpecl, lvds, or cmos references to 250 mhz programmable delays in path to pfd digital or analog lock detect, selectable 3 pairs of 1.6 ghz lvpecl outputs each output pair shares a 1-to-32 divider with coarse phase delay additive output jitter 225 fs rms channel-to-channel skew paired outputs of <10 ps automatic synchronization of all outputs on power-up manual synchronization of outputs as needed serial control port available in 48-lead lfcsp applications low jitter, low phase noise clock distribution clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 high performance instrumentation broadband infrastructure ate general description the ad9518-4 1 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on- chip pll and vco. the on-chip vco tunes from 1.45 ghz to 1.80 ghz. optionally, an external vco/vcxo of up to 2.4 ghz may be used. the ad9518-4 emphasizes low jitter and phase noise to maximize data converter performance, and can benefit other applications with demanding phase noise and jitter requirements. functional block diagram cp lf refin ref1 ref2 clk switchover and monitor pll divider and muxs vco status monitor lvpecl lvpecl out0 serial control port and digital logic ad9518-4 out1 out2 out3 out4 div/ out5 div/ div/ lvpecl 06433-001 figure 1. the ad9518-4 features six lvpecl outputs (in three pairs). the lvpecl outputs operate to 1.6 ghz. each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the ad9518-4 is available in a 48-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (vcp) to 5 v. a separate lvpecl power supply can be from 2.5 v to 3.3 v (nominal). the ad9518-4 is specified for operation over the industrial range of ?40c to +85c. 1 ad9518 is used throughout to refe r to all the members of the ad9518 family. however, when ad9518-4 is used, it is referring to that specific member of the ad9518 family.
ad9518-4 rev. a | page 2 of 64 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? power supply requirements ....................................................... 4 ? pll characteristics ...................................................................... 4 ? clock inputs .................................................................................. 6 ? clock outputs ............................................................................... 6 ? timing characteristics ................................................................ 6 ? clock output additive phase noise (distribution only; vco divider not used) .............................................................. 7 ? clock output absolute phase noise (internal vco used) .... 7 ? clock output absolute time jitter (clock generation using internal vco) .................................................................... 8 ? clock output absolute time jitter (clock cleanup using internal vco) .................................................................... 8 ? clock output absolute time jitter (clock generation using external vcxo) ................................................................ 8 ? clock output additive time jitter (vco divider not used) .............................................................................................. 9 ? clock output additive time jitter (vco divider used) ....... 9 ? serial control port ..................................................................... 10 ? pd , sync , and reset pins ..................................................... 10 ? ld, status, and refmon pins ............................................ 11 ? power dissipation ....................................................................... 11 ? timing diagrams ............................................................................ 12 ? absolute maximum ratings .......................................................... 13 ? thermal resistance .................................................................... 13 ? esd caution................................................................................ 13 ? pin configuration and function descriptions ........................... 14 ? typical performance characteristics ........................................... 16 ? terminology .................................................................................... 20 ? detailed block diagram ................................................................ 21 ? theory of operation ...................................................................... 22 ? operational configurations ...................................................... 22 ? digital lock detect (dld) ....................................................... 30 ? clock distribution ..................................................................... 34 ? reset modes ................................................................................ 38 ? power-down modes .................................................................. 38 ? serial control port ......................................................................... 40 ? serial control port pin descriptions ....................................... 40 ? general operation of serial control port ............................... 40 ? the instruction word (16 bits) ................................................ 41 ? msb/lsb first transfers ........................................................... 41 ? thermal performance .................................................................... 44 ? control registers ............................................................................ 45 ? control register map overview .............................................. 45 ? control register map descriptions ......................................... 47 ? applications information .............................................................. 60 ? frequency planning using the ad9518 .................................. 60 ? using the ad9518 outputs for adc clock applications .... 60 ? lvpecl clock distribution ..................................................... 61 ? outline dimensions ....................................................................... 62 ? ordering guide .......................................................................... 62 ?
ad9518-4 rev. a | page 3 of 64 revision history 1/10rev. 0 to rev. a added 48-lead lfcsp package (cp-48-8) .................... universal changes to features, applications, and general description ..... 1 change to cprset pin resistor parameter .................................. 4 changes to v cp supply parameter ................................................. 11 changes to table 18 ........................................................................ 13 added exposed paddle notation to figure 4; changes to table 19 ........................................................................ 14 change to high frequency clock distributionclk or external vco > 1600 mhz section; change to table 21 .......... 22 changes to table 23 ........................................................................ 24 change to configuration and register settings section ............ 25 change to phase frequency detector (pfd) section ................ 26 changes to charge pump (cp), on-chip vco, pll external loop filter, and pll reference inputs sections ......... 27 change to figure 31; added figure 32 ......................................... 27 changes to reference switchover and prescaler sections ......... 28 changes to a and b counters section and table 27 .................. 29 change to holdover section .......................................................... 31 changes to vco calibration section ........................................... 33 changes to clock distribution section ........................................ 34 change to table 32; change to channel frequency division (0, 1, and 2) section ........................................................ 35 change to write section ................................................................ 40 change to figure 46 ........................................................................ 42 added thermal performance section; added table 41 ............ 44 changes to 0x003 register address .............................................. 45 changes to table 43 ........................................................................ 47 changes to table 44 ........................................................................ 48 changes to table 45 ........................................................................ 55 changes to table 46 ........................................................................ 57 changes to table 47 ........................................................................ 58 changes to table 48 ........................................................................ 59 added frequency planning using the ad9518 section ............ 60 changes to lvds clock distribution section ............................ 61 changes to figure 52 and figure 54; added figure 53 .............. 61 added exposed paddle notation to outline dimensions; changes to ordering guide ........................................................... 62 9/07revision 0: initial version
ad9518-4 rev. a | page 4 of 64 specifications typical (typ) is given for v s = v s_lvpecl = 3.3 v 5%; v s v cp 5.25 v; t a = 25c; r set = 4.12 k; cp rset = 5.1 k, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. power supply requirements table 1. parameter min typ max unit test conditions/comments v s 3.135 3.3 3.465 v 3.3 v 5% v s_lvpecl 2.375 v s v nominally 2.5 v to 3.3 v 5% v cp v s 5.25 v nominally 3.3 v to 5.0 v 5% rset pin resistor 4.12 k sets intern al biasing currents; connect to ground cprset pin resistor 2.7 5.1 k sets internal cp current range, nominally 4.8 ma (cp_lsb = 600 a); actual current can be calculated by cp_lsb = 3.06/cprset; connect to ground bypass pin capacitor 220 nf bypass for internal ldo regulator; necessary for ldo stability; connect to ground pll characteristics table 2. parameter min typ max unit test conditions/comments vco (on-chip) frequency range 1450 1800 mhz see figure 11 vco gain (k vco ) 50 mhz/v see figure 6 tuning voltage (v t ) 0.5 v cp ? 0.5 v v cp v s when using internal vco; outside of this range, the cp spurs may increase due to cp up/down mismatch frequency pushing (open-loop) 1 mhz/v phase noise @ 100 khz offset ?109 dbc/hz f = 1625 mhz phase noise @ 1 mhz offset ?128 dbc/hz f = 1625 mhz reference inputs differential mode (refin, refin ) differential mode (can accommodate single-ended input by ac grounding undriven input) input frequency 0 250 mhz frequencies below about 1 mhz should be dc-coupled; be careful to match v cm (self-bias voltage) input sensitivity 250 mv p-p pll figure of merit (fom) increases with increasingslew rate; see figure 10 self-bias voltage, refin 1.35 1.60 1.75 v self-bias voltage of refin 1 self-bias voltage, refin 1.30 1.50 1.60 v self-bias voltage of refin 1 input resistance, refin 4.0 4.8 5.9 k self-biased 1 input resistance, refin 4.4 5.3 6.4 k self-biased 1 dual single-ended mode (ref1, ref2) two single-ended cmos-compatible inputs input frequency (ac-coupled) 20 250 mhz slew rate > 50 v/s input frequency (dc-coupled) 0 250 mhz slew rate > 50 v/s; cmos levels input sensitivity (ac-coupled) 0.8 v p-p should not exceed v s p-p input logic high 2.0 v input logic low 0.8 v input current ?100 +100 a input capacitance 2 pf each pin, refin/ refin (ref1/ref2) phase/frequency detector (pfd) pfd input frequency 100 mhz antiba cklash pulse width = 1.3 ns, 2.9 ns 45 mhz antibacklash pulse width = 6.0 ns antibacklash pulse width 1.3 ns register 0x017[1:0] = 01b 2.9 ns register 0x017[1:0] = 00b; register 0x17[1:0] = 11b 6.0 ns register 0x017[1:0] = 10b
ad9518-4 rev. a | page 5 of 64 parameter min typ max unit test conditions/comments charge pump (cp) i cp sink/source programmable high value 4.8 ma with cp rset = 5.1 k low value 0.60 ma absolute accuracy 2.5 % cp v = v cp /2 v cp rset range 2.7/10 k i cp high impedance mode leakage 1 na sink-and-source current matching 2 % 0.5 < cp v < v cp ? 0.5 v i cp vs. cp v 1.5 % 0.5 < cp v < v cp ? 0.5 v i cp vs. temperature 2 % cp v = v cp /2 v prescaler (part of n divider) prescaler input frequency p = 1 fd 300 mhz p = 2 fd 600 mhz p = 3 fd 900 mhz p = 2 dm (2/3) 600 mhz p = 4 dm (4/5) 1000 mhz p = 8 dm (8/9) 2400 mhz p = 16 dm (16/17) 3000 mhz p = 32 dm (32/33) 3000 mhz prescaler output frequency 300 mhz a, b counter input frequency (prescaler input frequency divided by p) pll divider delays see table 44 , register 0x019: r, bits[5:3]; n, bits[2:0] 000 off 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps noise characteristics in-band phase noise of the charge pump/phase frequency detector (in-band is within the lbw of the pll) the pll in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 log(n) (where n is the value of the n divider) @ 500 khz pfd frequency ?165 dbc/hz @ 1 mhz pfd frequency ?162 dbc/hz @ 10 mhz pfd frequency ?151 dbc/hz @ 50 mhz pfd frequency ?143 dbc/hz pll figure of merit (fom) ?220 dbc/hz reference slew rate > 0.25 v/ns; fom +10 log(f pfd ) is an approximation of the pfd/cp in-band phase noise (in the flat region) inside the pll loop bandwidth; when running closed loop, the phase noise, as observed at the vco output, is increased by 20 log(n) pll digital lock detect window 2 signal available at ld, status, and refmon pins when selected by appropriate register settings required to lock (coincidence of edges) selected by register 0x017[1:0] and register 0x018[4] low range (abp 1.3 ns, 2.9 ns) 3.5 ns register 0x017[1:0] = 00b, 01b,11b; register 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 7.5 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 0b high range (abp 6 ns) 3.5 ns register 0x017[1:0] = 10b; register 0x018[4] = 0b to unlock after lock (hysteresis) 2 low range (abp 1.3 ns, 2.9 ns) 7 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 15 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 0b high range (abp 6 ns) 11 ns register 0x017[1:0] = 10b; register 0x018[4] = 0b 1 refin and refin self-bias points are offset slightly to av oid chatter on an open input condition. 2 for reliable operation of the digital lock detect, the period of the pfd frequency must be greater than the unlock-after-lock time.
ad9518-4 rev. a | page 6 of 64 clock inputs table 3. parameter min typ max unit test conditions/comments clock inputs (clk, clk ) differential input input frequency 0 1 2.4 ghz high frequency distribution (vco divider) 0 1 1.6 ghz distribution only (vco divider bypassed) input sensitivity, differential 150 mv p-p measured at 2.4 ghz; jitter performance is improved with slew rates > 1 v/ns input level, differential 2 v p-p larger voltage swings may turn on the protection diodes and may degrade jitter performance input common-mode voltage, v cm 1.3 1.57 1.8 v self-biased; enables ac coupling input common-mode range, v cmr 1.3 1.8 v with 200 mv p-p signal applied; dc-coupled input sensitivity, single-ended 150 mv p-p clk ac-coupled; clk ac-bypassed to rf ground input resistance 3.9 4.7 5.7 k self-biased input capacitance 2 pf 1 below about 1 mhz, the input should be dc-coupled. care should be taken to match v cm . clock outputs table 4. parameter min typ max unit test conditions/comments lvpecl clock outputs termination = 50 to v s ? 2 v out0, out1, out2, out3, out4, out5 differential (out, out ) output frequency, maximum 2950 mhz us ing direct to output; see figure 16 output high voltage (v oh ) v s ? 1.12 v s ? 0.98 v s ? 0.84 v output low voltage (v ol ) v s ? 2.03 v s ? 1.77 v s ? 1.49 v output differential voltage (v od ) 550 790 980 mv timing characteristics table 5. parameter min typ max unit test conditions/comments lvpecl termination = 50 to v s ? 2 v; level = 810 mv output rise time, t rp 70 180 ps 20% to 80%, measured differentially output fall time, t fp 70 180 ps 80% to 20%, measured differentially propagation delay, t pecl , clk-to-lvpecl output high frequency clock distribution configuration 835 995 1180 ps see figure 27 clock distribution configuration 773 933 1090 ps see figure 29 variation with temperature 0.8 ps/c output skew, lvpecl outputs 1 lvpecl outputs that share the same divider 5 15 ps lvpecl outputs on different dividers 13 40 ps all lvpecl outputs across multiple parts 220 ps 1 this is the difference between any two similar delay pa ths while operating at the s ame voltage and temperature.
ad9518-4 rev. a | page 7 of 64 clock output additive phase noise (distribution only; vco divider not used) table 6. parameter min typ max unit test conditions/comments clk-to-lvpecl additive phase noise distribution section only; does not include pll and vco clk = 1 ghz, output = 1 ghz input slew rate > 1 v/ns divider = 1 @ 10 hz offset ?109 dbc/hz @ 100 hz offset ?118 dbc/hz @ 1 khz offset ?130 dbc/hz @ 10 khz offset ?139 dbc/hz @ 100 khz offset ?144 dbc/hz @ 1 mhz offset ?146 dbc/hz @ 10 mhz offset ?147 dbc/hz @ 100 mhz offset ?149 dbc/hz clk = 1 ghz, output = 200 mhz input slew rate > 1 v/ns divider = 5 @ 10 hz offset ?120 dbc/hz @ 100 hz offset ?126 dbc/hz @ 1 khz offset ?139 dbc/hz @ 10 khz offset ?150 dbc/hz @ 100 khz offset ?155 dbc/hz @ 1 mhz offset ?157 dbc/hz >10 mhz offset ?157 dbc/hz clock output absolute phase noise (internal vco used) table 7. parameter min typ max unit test conditions/comments lvpecl absolute phase noise inte rnal vco; direct to lvpecl output vco = 1800 mhz; output = 1800 mhz @ 1 khz offset ?47 dbc/hz @ 10 khz offset ?82 dbc/hz @ 100 khz offset ?106 dbc/hz @ 1 mhz offset ?125 dbc/hz @ 10 mhz offset ?142 dbc/hz @ 40 mhz offset ?146 dbc/hz vco = 1625 mhz; output = 1625 mhz @ 1 khz offset ?55 dbc/hz @ 10 khz offset ?85 dbc/hz @ 100 khz offset ?109 dbc/hz @ 1 mhz offset ?128 dbc/hz @ 10 mhz offset ?143 dbc/hz @ 40 mhz offset ?147 dbc/hz vco = 1450 mhz; output = 1450 mhz @ 1 khz offset ?61 dbc/hz @ 10 khz offset ?90 dbc/hz @ 100 khz offset ?113 dbc/hz @ 1 mhz offset ?131 dbc/hz @ 10 mhz offset ?144 dbc/hz @ 40 mhz offset ?148 dbc/hz
ad9518-4 rev. a | page 8 of 64 clock output absolute time jitter (clock generation using internal vco) table 8. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup where the reference source is clean, so a wider pll loop bandwidth is used; reference = 15.36 mhz; r = 1 vco = 1475 mhz; lvpecl = 491.52 mhz; pll lbw = 135 khz 135 fs rms integration bw = 200 khz to 10 mhz 275 fs rms integration bw = 12 khz to 20 mhz vco = 1475 mhz; lvpecl = 122.88 mhz; pll lbw = 135 khz 145 fs rms integration bw = 200 khz to 10 mhz 275 fs rms integration bw = 12 khz to 20 mhz vco = 1475 mhz; lvpecl = 61.44 mhz; pll lbw = 135 khz 170 fs rms integration bw = 200 khz to 10 mhz 305 fs rms integration bw = 12 khz to 20 mhz clock output absolute time jitter (clock cleanup using internal vco) table 9. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup where the reference source is jittery, so a narrower pll loop bandwidth is used; reference = 10.0 mhz; r = 20 vco = 1555 mhz; lvpecl = 155.52 mhz; pll lbw = 500 hz 500 fs rms integration bw = 12 khz to 20 mhz vco = 1475 mhz; lvpecl = 122.88 mhz; pll lbw = 500 hz 400 fs rms integration bw = 12 khz to 20 mhz clock output absolute time jitter (clock generation using external vcxo) table 10. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 245.76 mhz vcxo (toyocom tco-2112); reference = 15.36 mhz; r = 1 lvpecl = 245.76 mhz; pll lbw = 125 hz 54 fs rms integration bw = 200 khz to 5 mhz 77 fs rms integration bw = 200 khz to 10 mhz 109 fs rms integration bw = 12 khz to 20 mhz lvpecl = 122.88 mhz; pll lbw = 125 hz 79 fs rms integration bw = 200 khz to 5 mhz 114 fs rms integration bw = 200 khz to 10 mhz 163 fs rms integration bw = 12 khz to 20 mhz lvpecl = 61.44 mhz; pll lbw = 125 hz 124 fs rms integration bw = 200 khz to 5 mhz 176 fs rms integration bw = 200 khz to 10 mhz 259 fs rms integration bw = 12 khz to 20 mhz
ad9518-4 rev. a | page 9 of 64 clock output additive time jitter (vco divider not used) table 11. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only ; does not include pll and vco; uses rising edge of clock signal clk = 622.08 mhz; lvpecl = 622.08 mhz; divider = 1 40 fs rms bw = 12 khz to 20 mhz clk = 622.08 mhz; lvpecl = 155.52 mhz; divider = 4 80 fs rms bw = 12 khz to 20 mhz clk = 1.6 ghz; lvpecl = 100 mhz; divider = 16 215 fs rms calculated from snr of adc method; dcc not used for even divides clk = 500 mhz; lvpecl = 100 mhz; divider = 5 245 fs rms calculated from snr of adc method; dcc on clock output additive time jitter (vco divider used) table 12. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only; does not include pll and vco; uses rising edge of clock signal clk = 2.4 ghz; vco div = 2; lvpecl = 100 mhz; divider = 12; duty-cycle correction = off 210 fs rms calculated from snr of adc method
ad9518-4 rev. a | page 10 of 64 serial control port table 13. parameter min typ max unit test conditions/comments cs (input) cs has an internal 30 k pull-up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 3 a input logic 0 current 110 a input capacitance 2 pf sclk (input) sclk has an internal 30 k pull-down resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 110 a input logic 0 current 1 a input capacitance 2 pf sdio (when input) input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 10 na input logic 0 current 20 na input capacitance 2 pf sdio, sdo (outputs) output logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t high 16 ns pulse width low, t low 16 ns sdio to sclk setup, t ds 2 ns sclk to sdio hold, t dh 1.1 ns sclk to valid sdio and sdo, t dv 8 ns cs to sclk setup and hold, t s , t h 2 ns cs minimum pulse width high, t pwh 3 ns pd , sync , and reset pins table 14. parameter min typ max unit test conditions/comments input characteristics these pins each have a 30 k internal pull-up resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 110 a logic 0 current 1 a capacitance 2 pf reset timing pulse width low 50 ns sync timing pulse width low 1.5 high speed clock cycles high speed clock is clk input signal
ad9518-4 rev. a | page 11 of 64 ld, status, and refmon pins table 15. parameter min typ max unit test conditions/comments output characteristics when selected as a digital output (cmos); there are other modes in which these pins are not cmos digital outputs; see table 44 , register 0x017, register 0x01a, and register 0x01b output voltage high (v oh ) 2.7 v output voltage low (v ol ) 0.4 v maximum toggle rate 100 mhz applies when mux is set to an y divider or counter output, or pfd up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling analog lock detect capacitance 3 pf on-chip capacitance; used to calculate rc time constant for analog lock detect readback; use a pull-up resistor ref1, ref2, and vco frequency status monitor normal range 1.02 mhz frequency above which the monitor indicates the presence of the reference extended range (ref1 and ref2 only) 8 khz frequency above which the monitor indicates the presence of the reference ld pin comparator trip point 1.6 v hysteresis 260 mv power dissipation table 16. parameter min typ max unit test conditions/comments power dissipation, chip power-on default 0.76 1.0 w no clock; no programming; default register values; does not include power dissipated in external resistors full operation 1.1 1.7 w pll on; internal vco = 1625 mhz; vco divider = 2; all channel dividers on; six lvpecl outputs @ 406 mhz; does not include power dissipated in external resistors pd power-down 75 185 mw pd pin pulled low; does not include power dissipated in terminations pd power-down, maximum sleep 31 mw pd pin pulled low; pll power-down 0x10<1:0> = 01b; sync power-down 0x230<2> = 1b; ref for distribution power-down 0x230<1> = 1b v cp supply 4 4.8 mw pll operating; typical closed-lo op configuration power deltas, individual functions power delta when a function is enabled/disabled vco divider 30 mw vco divider not used refin (differential) 20 mw all references off to differential reference enabled ref1, ref2 (single-ended) 4 mw all references off to ref1 or ref2 enabled; differential reference not enabled vco 70 mw clk input selected to vco selected pll 75 mw pll off to pll on, normal operation; no reference enabled channel divider 30 mw divider bypassed to divide-by-2 to divide-by-32 lvpecl channel (divider plus output driver) 160 mw no lvpecl output on to one lvpecl output on lvpecl driver 90 mw second lvpecl output turned on, same channel
ad9518-4 rev. a | page 12 of 64 timing diagrams differential lvpecl 80% 20% t rp cl k t clk t pecl 06433-060 figure 2. clk/ clk to clock output timing, div = 1 t fp 06433-061 figure 3. lvpecl timing, differential
ad9518-4 rev. a | page 13 of 64 absolute maximum ratings table 17. parameter rating vs, vs_lvpecl to gnd ?0.3 v to +3.6 v vcp to gnd ?0.3 v to +5.8 v refin, refin to gnd ?0.3 v to v s + 0.3 v refin to refin ?3.3 v to +3.3 v rset to gnd ?0.3 v to v s + 0.3 v cprset to gnd ?0.3 v to v s + 0.3 v clk, clk to gnd ?0.3 v to v s + 0.3 v clk to clk ?1.2 v to +1.2 v sclk, sdio, sdo, cs to gnd ?0.3 v to v s + 0.3 v out0, out0 , out1, out1 , out2, out2 , out3, out3 ,out4, out4 , out5, out5 to gnd ?0.3 v to v s + 0.3 v sync to gnd ?0.3 v to v s + 0.3 v refmon, status, ld to gnd ?0.3 v to v s + 0.3 v junction temperature 1 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c 1 see table 18 for ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 18. package type 1 ja unit 48-lead lfcsp 24.7 c/w 1 thermal impedance measurem ents were taken on a 4- layer board in still air in accordance with eia/jesd51-2. esd caution
ad9518-4 rev. a | page 14 of 64 vs pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 sclk cs sdo sdio reset pd out4 out4 _lvpecl out5 out5 vs 48 47 46 45 44 43 42 41 40 39 38 37 refin (ref1) refin (ref2) cprset vs rset vs out0 out0 vs_lvpecl out1 out1 vs 1 2 3 4 5 6 7 8 9 10 11 12 35 36 34 33 32 31 30 29 28 27 26 25 ad9518-4 top view (not to scale) pin 1 indicator cp status clk vcp refmon ld bypass vs ref_sel lf sync clk out3 out2 v s v s vs_lvpecl vs_lvpecl out3 out2 n c g n d v s g n d 433-003 06 notes 1. nc = no connect. 2. the external paddle on the bottom of the package must be connected to ground for proper operation. figure 4. pin configuration table 19. pin function descriptions pin no. input/ output pin type mnemonic description 1 i 3.3 v cmos refmon reference monitor (output). this pin has multiple selectable outputs; see table 44 , register 0x1b. 2 o 3.3 v cmos ld lock detect (output). this pin has multiple selectable outputs; see table 44 , register 0x1a. 3 i power vcp power supply for charge pump (cp). v s v cp 5.0 v. 4 o cp charge pump (output). connects to external loop filter. 5 o 3.3 v cmos status status (output). this pin has multiple selectable outputs; see table 44 , register 0x17. 6 i 3.3 v cmos ref_sel reference select. selects ref1 (low) or ref2 (high). this pin has an internal 30 k pull-down resistor. 7 i 3.3 v cmos sync manual synchronizations and manual ho ldover. this pin initiates a manual synchronization and is also used for manual holdover. active low. this pin has an internal 30 k pull-up resistor. 8 i loop filter lf loop filter (input). connects to vco control voltage node internally. this pin has 31 pf of internal capacitance to ground, which may influence the loop filter design for large loop bandwidths. 9 o loop filter bypass this pin is for bypassing the ldo to ground with a capacitor. 10, 24, 25, 26, 35, 37, 43, 45 i power vs 3.3 v power pins. along with clk , this is the self-biased differential input for the clock distribution section. 11 i differential clock input clk 12 i differential clock input clk along with clk, this is the self-biased differential input for the clock distribution section.
ad9518-4 rev. a | page 15 of 64 pin no. input/ output pin type mnemonic description 13 i 3.3 v cmos sclk serial control port data clock signal. 14 i 3.3 v cmos cs serial control port chip select, active low. this pin has an internal 30 k pull-up resistor. 15 o 3.3 v cmos sdo serial control port unidirectional serial data out. 16 i/o 3.3 v cmos sdio serial control po rt bidirectional serial data in/out. 17 i 3.3 v cmos reset chip reset, active low. this pin has an internal 30 k pull-up resistor. 18 i 3.3 v cmos pd chip power down, active low. this pin has an internal 30 k pull-up resistor. 19 o lvpecl out4 lvpecl output; one side of a differential lvpecl output. 20 o lvpecl out4 lvpecl output; one side of a differential lvpecl output. 21, 30, 31, 40 i power vs_lvpecl extended voltage 2.5 v to 3.3 v lvpecl power pins. 22 o lvpecl out5 lvpecl output; one side of a differential lvpecl output. 23 o lvpecl out5 lvpecl output; one side of a differential lvpecl output. 27, 34 gnd gnd ground. see the description for epad. 28 o lvpecl out3 lvpecl output; one side of a differential lvpecl output. 29 o lvpecl out3 lvpecl output; one side of a differential lvpecl output. 32 o lvpecl out2 lvpecl output; one side of a differential lvpecl output. 33 o lvpecl out2 lvpecl output; one side of a differential lvpecl output. 36 nc no connection. 38 o lvpecl out1 lvpecl output; one side of a differential lvpecl output. 39 o lvpecl out1 lvpecl output; one side of a differential lvpecl output. 41 o lvpecl out0 lvpecl output; one side of a differential lvpecl output. 42 o lvpecl out0 lvpecl output; one side of a differential lvpecl output. 44 o current set resistor rset resistor connected here sets internal bias currents. nominal value = 4.12 k. 46 o current set resistor cprset resistor connected here sets the cp current range. nominal value = 5.1 k. 47 i reference input refin (ref2) along with refin, this is the (self-biased) differenti al input for the pll reference. alternatively, this pin is a single-ended input for ref2. 48 i reference input refin (ref1) along with refin , this is the (self-biased) differen tial input for the pll reference. alternatively, this pin is a single-ended input for ref1. epad gnd gnd ground. the external paddle on the bottom of the package must be connected to ground for proper operation.
ad9518-4 rev. a | page 16 of 0 500 1000 1500 2000 2500 3000 frequency (mhz) typical performance characteristics current (ma) 300 100 120 140 160 180 200 220 240 260 280 3 channels?6 lvpecl 3 channels?3 lvpecl 2 channels?2 lvpecl 1 channel?1 lvpecl 64 06433-007 1.45 1.55 1.65 1.75 vco frequency (ghz) figure 5. current vs. frequency, direct-to-output, lvpecl outputs 50 20 25 30 35 40 45 k vco (mhz/v) 06433-200 0 0.5 1.0 1.5 2.0 2.5 3.0 voltage on cp pin (v) figure 6. k vco vs. vco frequency 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 current from cp pin (ma) pump down pump up 06433-011 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 3.0 4.0 2.5 3.5 5.04.5 current from cp pin (ma) voltage on cp pin (v) figure 7. charge pump characteristics @ v cp = 3.3 v pump down pump up 06433-012 figure 8. charge pump characteristics @ v cp = 5.0 v ? 140 ?145 ?150 ?155 ?160 ?165 ?170 0.1 1 100 10 pfd phase noise referred to pfd input (dbc/hz) pfd frequency (mhz) 06433-013 figure 9. pfd phase noise referred to pfd input vs. pfd frequency ? 210 ?224 ?222 ?220 ?218 ?216 ?214 ?212 02 . 5 2.0 1.5 1.0 0.5 pll figure of merit (dbc/hz) slew rate (v/ns) 06433-136 figure 10. pll figure of merit (fom) vs. slew rate at refin/ refin
ad9518-4 rev. a | page 17 of 2.1 0.9 1.1 1.3 1.5 1.7 1.9 vco tuning voltage (v) 64 1.45 1.55 1.65 1.75 1.50 1.60 1.70 1.80 frequency (ghz) 06433-20 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 0 relative power (db) 1 ?110 ?100 ?90 figure 11. vco tuning voltage vs. frequency center 122.88mhz span 50mhz 5mhz/div 0643 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 0 relative power (db) 3-202 ?110 ?100 ?90 center 122.88mhz span 1mhz 100khz/div figure 12. pfd/cp spurs; 122.88 mhz; pfd = 15.36 mhz; lbw = 135 khz; i cp = 3 ma; f vco = 1.475 ghz 06433-203 1.0 0.6 0.2 ?0.2 ?0.6 ?1.0 02 5 20 15 10 5 differential output (v) time (ns) figure 13. output spectrum, lvpecl; 122.88 mhz; pfd = 15.36 mhz; lbw = 135 khz; i cp = 3 ma; f vco = 1.475 ghz 06433-014 1.0 0.6 0.2 ?0.2 ?0.6 ?1.0 02 1 differential output (v) time (ns) figure 14. lvpecl output (differential) @ 100 mhz 06433-015 1600 800 1000 1200 1400 differential swing (mv p-p) figure 15. lvpecl output (differential) @ 1600 mhz 03 2 1 frequency (ghz) 06433-02 0 figure 16. lvpecl differential swing vs. frequency
ad9518-4 rev. a | page 18 of 64 ? 80 ?100 ?120 ?90 ?110 ?130 ?140 phase noise (dbc/hz) ? 120 ?130 ?125 ?135 ?140 ?145 ?150 ?155 ?160 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) ?150 10k 100m 10m 1m 100k frequency (hz) 06433-20 5 figure 17. internal vco phase noise (absolute) direct to lvpecl @1800 mhz ? 80 ?100 ?120 ?90 ?110 ?130 ?140 phase noise (dbc/hz) 06433-026 figure 20. phase noise (additive) lvpecl @ 245.76 mhz, divide-by-1 ? 110 ?120 ?130 ?140 ?150 ?160 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) ?150 10k 100m 10m 1m 10k frequency (hz) 06433-20 6 figure 18. internal vco phase noise (absolute) direct to lvpecl @ 1625 mhz ? 80 ?100 ?120 ?90 ?110 ?130 ?140 phase noise (dbc/hz) 06433-027 figure 21. phase noise (additive) lvpecl @ 200 mhz, divide-by-5 ? 100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) 10 100m 10m 1m 100k 10k 1k 100 frequency (hz) 06433-12 ?150 10k 100m 10m 1m 100k frequency (hz) 06433-207 figure 19. internal vco phase noise (absolute) direct to lvpecl @ 1450 mhz 8 figure 22. phase noise (additive) lvpecl @ 1600 mhz, divide-by-1
ad9518-4 rev. a | page 19 of 64 ? 120 ?150 ?140 ?130 ? 120 ?160 ?150 ?140 ?130 1k 100m 10m 1m 100k 10k phase noise (dbc/hz) frequency (hz) ?160 phase noise (dbc/hz) 1k 100m 10m 1m 100k 10k frequency (hz) 06433-20 8 figure 23. phase noise (absolute) clock generation; internal vco @ 1.475 ghz; pfd = 15.36 mhz; lbw = 135 khz; lvpecl output = 122.88 mhz ? 90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) 06433-140 figure 25. phase noise (absolute); external vcxo (toyocom tco-2112) @ 245.76 mhz; pfd = 15.36 mhz; lbw = 250 hz; lvpecl output = 245.76 mhz ?160 1k 100m 10m 1m 100k 10k frequency (hz) 06433-209 figure 24. phase noise (absolute) clock cleanup; internal vco @ 1.556 ghz; pfd = 19.44 mhz; lbw = 12.8 khz; lvpecl output = 155.52 mhz
ad9518-4 rev. a | page 20 of 64 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs, dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal-to-noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9518-4 rev. a | page 21 of 64 detailed block diagram ref_ sel v s gnd programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9518-4 status status r divider vco status programmable r delay reference switchover cprset v cp rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) vco phase frequency detector lock detect pll reference hold charge pump out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 divide by 2, 3, 4, 5, or 6 01 out4 out5 out4 out5 lvpecl divide by 1 to 32 pd sync reset sclk sdio sdo digital logic serial control port cs 06433-002 figure 26. detailed block diagram
ad9518-4 rev. a | page 22 of 64 theory of operation operational configurations the ad9518 can be configured in several ways. these configurations must be set up by loading the control registers (see table 42 and table 43 through tabl e 49 ). each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. high frequency clock distributionclk or external vco > 1600 mhz the ad9518 power-up default configuration has the pll powered off and the routing of the input set so that the clk/ clk input is connected to the distribution section through the vco divider (divide-by-2/ divide-by-3/divide-by-4/ divide-by-5/divide-by-6). this is a distribution-only mode that allows for an external input up to 2.4 ghz (see ). the maximum frequency that can be applied to the channel dividers is 1600 mhz; therefore, higher input frequencies must be divided down before reaching the channel dividers. this input routing can also be used for lower input frequencies, but the minimum divide is 2 before the channel dividers. table 3 when the pll is enabled, this routing also allows the use of the pll with an external vco or vcxo with a frequency of less than 2400 mhz. in this configuration, the internal vco is not used and is powered off. the external vco/vcxo feeds directly into the prescaler. the register settings shown in table 20 are the default values of these registers at power-up or after a reset operation. if the contents of the registers are altered by prior programming after power-up or reset, these registers can also be set intentionally to these values. after the appropriate register values are programmed, register 0x232 must be set to 0x01 for the values to take effect. table 20. default settings of some pll registers register function 0x010[1:0] = 01b pll asynchronous power-down (pll off ). 0x1e0[2:0] = 010b set vco divider = 4. 0x1e1[0] = 0b use the vco divider. 0x1e1[1] = 0b clk selected as the source. when using the internal pll with an external vco, the pll must be turned on. table 21. settings when using an external vco register function 0x010[1:0] = 00b pll normal operation (pll on). 0x010 to 0x01e pll settings. select and enable a reference input; set r, n (p, a, b), pfd polarity, and i cp , according to the intended loop configuration. 0x1e1[1] = 0b clk selected as the source. an external vco requires an external loop filter that must be connected between cp and the tuning pin of the vco. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco being used. table 22. setting the pfd polarity register function 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency). 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency).
ad9518-4 rev. a | page 23 of 64 programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9518-4 status status r divider vco status programmable r delay reference switchover ref_ sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) vco phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 01 divide by 2, 3, 4, 5, or 6 pd sync reset sclk sdio sdo cs digital logic serial control port out4 out5 out5 out4 lvpecl divide by 1 to 32 06433-029 figure 27. high frequency clock distribution or external vco >1600 mhz
ad9518-4 rev. a | page 24 of 64 internal vco and clock distribution when using the internal vco and pll, the vco divider must be employed to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (1.6 ghz, see table 3 ). the internal pll uses an external loop filter to set the loop bandwidth. the external loop filter is also crucial to the loop stability. when using the internal vco, it is necessary to calibrate the vco (register 0x018[0]) to ensure optimal performance. for internal vco and clock distribution applications, the register settings shown in table 23 should be used. table 23. settings when using internal vco register function 0x010[1:0] = 00b pll normal operation (pll on). 0x010 to 0x01e pll settings. select and enable a reference input; set r, n (p, a, b), pfd polarity, and i cp according to the intended loop configuration. 0x018[0] = 0b, 0x232[0] = 1b reset vco calibration. this process is not required the first time after power-up, but it must be performed subsequently. 0x1e0[2:0] set vco divider to divide-by-2, divide-by-3, divide-by-4, divide-by-5, or divide-by-6. 0x1e1[0] = 0b use the vco divider as source for the distribution section. 0x1e1[1] = 1b select vco as the source. 0x018[0] = 1b, 0x232[0] = 1b initiate vco calibration. ref_ sel v s gnd programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 status status r divider vco status programmable r delay reference switchover cprset v cp rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) vco phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 01 divide by 2, 3, 4, 5, or 6 pd sync reset sclk sdio sdo cs digital logic serial control port out4 out5 out4 out5 lvpecl divide by 1 to 32 06433-030 ad9518-4 figure 28. internal vco and clock distribution
ad9518-4 rev. a | page 25 of 64 programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9518-4 status status r divider vco status programmable r delay reference switchover ref_ sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) vco phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 divide by 1 to 32 01 pd sync reset sclk sdio sdo cs digital logic serial control port divide by 2, 3, 4, 5, or 6 06433-028 out4 out5 out5 out4 lvpecl figure 29. clock distribution or external vco <1600 mhz clock distribution or external vco < 1600 mhz when the external clock source to be distributed or the external vco/vcxo is <1600 mhz, a configuration that bypasses the vco divider can be used. this differs from the high frequency clock distributionclk or external vco > 1600 mhz section only in that the vco divider (divide-by-2/divide-by-3/ divide-by-4/divide-by-5/divide-by-6) is bypassed. this limits the frequency of the clock source to <1600 mhz (due to the maximum input frequency allowed at the channel dividers). configuration and register settings for clock distribution applications where the external clock is <1600 mhz, the register settings shown in table 24 should be used. table 24. settings for clock distribution < 1600 mhz register function 0x010[1:0] = 01b pll asynchronous power-down (pll off ) 0x1e1[0] = 1b bypass the vco divider as source for distribution section 0x1e1[1] = 0b clk selected as the source when using the internal pll with an external vco < 1600 mhz, the pll must be turned on. table 25. settings for using internal pll with external vco < 1600 mhz register function 0x1e1[0] = 1b bypass the vco divider as source for distribution section 0x010[1:0] = 00b pll normal operation (pll on) along with other appropriate pll settings in register 0x010 to register 0x01e an external vco/vcxo requires an external loop filter that must be connected between cp and the tuning pin of the vco/vcxo. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco/vcxo being used. table 26. setting the pfd polarity register function 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency) after the appropriate register values are programmed, register 0x232 must be set to 0x01 for the values to take effect.
ad9518-4 rev. a | page 26 of 64 phase-locked loop (pll) clk charge pump r divider cp v cp v sgnd status cprset dist ref rset divide by 2, 3, 4, 5, or 6 a/b counters ld n divider refmon lf bypass ref_sel low dropout regulator (ldo) 01 0 1 ref2 ref1 reference switchover vco p, p + 1 prescaler hold lock detect status vco status status clk phase frequency detector programmable r delay programmable n delay pll ref refin (ref1) refin (ref2) 06433-064 figure 30. pll functional blocks the ad9518 includes an on-chip pll with an on-chip vco. the pll blocks can be used either with the on-chip vco to create a complete phase-locked loop, or with an external vco or vcxo. the pll requires an external loop filter, which usually consists of a small number of capacitors and resistors. the configuration and components of the loop filter help to establish the loop bandwidth and stability of the operating pll. the ad9518 pll is useful for generating clock frequencies from a supplied reference frequency. this includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. in addition, the pll can be exploited to clean up jitter and phase noise on a noisy reference. the exact choices of pll parameters and loop dynamics are application specific. the flexibility and depth of the ad9518 pll allow the part to be tailored to function in many different applications and signal environments. configuration of the pll the ad9518 allows flexible configuration of the pll, accommodating various reference frequencies, pfd comparison frequencies, vco frequencies, internal or external vco/vcxo, and loop dynamics. this is accomplished by the various settings that include the r divider, the n divider, the pfd polarity (only applicable to external vco/vcxo), the antibacklash pulse width, the charge pump current, the selection of internal vco or external vco/vcxo, and the loop bandwidth. these are managed through programmable register settings (see table 42 and table 44 ) and by the design of the external loop filter. successful pll operation and satisfactory pll loop performance are highly dependent upon proper configuration of the pll settings. the design of the external loop filter is crucial to the proper operation of the pll. a thorough knowledge of pll theory and design is helpful. adisimclk ? (v1.2 or later) is a free program that can help with the design and exploration of the capabilities and features of the ad9518, including the design of the pll loop filter. it is available at www.analog.com/clocks . phase frequency detector (pfd) the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the antibacklash pulse width is set by register 0x017[1:0]. an important limit to keep in mind is the maximum frequency allowed into the pfd, which in turn determines the correct antibacklash pulse setting. the antibacklash pulse setting is specified in the phase/frequency detector parameter of table 2 .
ad9518-4 rev. a | page 27 of 64 charge pump (cp) ad9518-4 the charge pump is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs, and tells the cp to pump up or pump down to charge or discharge the integrating node (part of the loop filter). the integrated and filtered cp current is transformed into a voltage that drives the tuning node of the internal vco through the lf pin (or the tuning pin of an external vco) to move the vco frequency up or down. the cp can be set (register 0x010[6:4]) for high impedance (allows holdover operation), for normal operation (attempts to lock the pll loop), for pump up, or for pump down (test modes). the cp current is programmable in eight steps from (nominally) 600 a to 4.8 ma. the exact value of the cp current lsb is set by the cprset resistor, which is nominally 5.1 k. if the value of the resistor connected to the cp_rset pin is doubled, the resulting charge pump current range becomes 300 a to 2.4 ma. on-chip vco the ad9518 includes a low noise, on-chip vco covering the frequency range shown in table 2 . the calibration procedure ensures that the vco operating voltage is centered for the desired vco frequency. the vco must be calibrated when the pll loop is first set up, as well as any time the nominal vco frequency changes. however, once the vco is calibrated, the vco has sufficient operating range to stay locked over temperature and voltage extremes without needing additional calibration. see the vco calibration section for more information. the on-chip vco is powered by an on-chip, low dropout (ldo), linear voltage regulator. the ldo provides some isolation of the vco from variations in the power supply voltage level. the bypass pin should be connected to ground by a 220 nf capacitor to ensure stability. this ldo employs the same technology used in the anycap? line of regulators from analog devices, inc., making it insensitive to the type of capacitor used. driving an external load from the bypass pin is not supported. note that the reference input signal must be present and the vco divider must not be static during vco calibration. pll external loop filter when using the internal vco, the external loop filter should be referenced to the bypass pin for optimal noise and spurious performance. an example of an external loop filter for a pll that uses the internal vco is shown in figure 31 . the third- order design that is shown in figure 31 usually offers the best performance. a loop filter must be calculated for each desired pll configuration. the values of the components depend upon the vco frequency, the k vco , the pfd frequency, the cp current, the desired loop bandwidth, and the desired phase margin. the loop filter affects the phase noise, the loop settling time, and the loop stability. a basic knowledge of pll theory is helpful for under- standing loop filter design. adisimclk can help with the calculation of a loop filter according to the application requirements. lf vco charge pump cp bypass c1 c2 c3 r1 31pf r2 c bp = 220nf 06433-065 figure 31. example of external loop filter for pll using the internal vco when using an external vco, the external loop filter should be referenced to ground. an example of an external loop filter for a pll using an external vco is shown in figure 32 . clk/clk external vco/vcxo charge pump ad9518-4 cp c1 c2 c3 r1 r2 06433-265 figure 32. example of external loop filter for a pll using an external vco pll reference inputs the ad9518 features a flexible pll reference input circuit that allows either a fully differential input or two separate single-ended inputs. the input frequency range for the reference inputs is specified in table 2 . both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals. the differential input and the single-ended inputs share the two pins, refin (ref1)/ refin (ref2). the desired reference input type is selected and controlled by register 0x01c (see and ). tabl e 42 table 44 when the differential reference input is selected, the self-bias level of the two sides is offset slightly (~100 mv, see table 2 ) to prevent chattering of the input buffer when the reference is slow or missing. this increases the voltage swing required of the driver and overcomes the offset. the differential reference input can be driven by either ac-coupled lvds or ac-coupled lvpecl signals. the single-ended inputs can be driven by either a dc-coupled cmos level signal or an ac-coupled sine-wave or square wave. each single-ended input can be independently powered down when not needed to increase isolation and reduce power. either a differential or a single-ended reference must be specifically enabled. all pll reference inputs are off by default. the differential reference input is powered down whenever the pll is powered down, or when the differential reference input is not selected. the single-ended buffers power down when the pll is powered down and when their individual power down registers are set. when the differential mode is selected, the single-ended inputs are powered down.
ad9518-4 rev. a | page 28 of 64 in differential mode, the reference input pins are internally self- biased so that they can be ac-coupled via capacitors. it is possible to dc couple to these inputs. if the differential refin is driven by a single-ended signal, the unused side ( refin ) should be decoupled via a suitable capacitor to a quiet ground. shows the refin equivalent circuit. figure 33 v s ref1 ref2 refin 150? 150? 10k ? 12k ? 10k ? 10k ? refin 85k ? v s 85k ? v s 06433-066 figure 33. refin eq uivalent circuit reference switchover the ad9518 supports dual single-ended cmos inputs, as well as a single differential reference input. in the dual single-ended reference mode, the ad9518 supports automatic and manual pll reference clock switching between ref1 (on pin refin) and ref2 (on pin refin ). this feature supports networking and other applications that require hitless switching of redundant references. when used in conjunction with the automatic holdover function, the ad9518 can achieve a worst-case reference input switchover with an output frequency disturbance as low as 10 ppm. when using reference switchover, the single-ended reference inputs should be dc-coupled cmos levels and never be allowed to go to high impedance. if these inputs are allowed to go to high impedance, noise may cause the buffer to chatter, causing a false detection of the presence of a reference. t here are several configurable modes of reference switchover. the switchover can be performed manually or automatically. manual switchover is performed either through register 0x01c or by using the ref_sel pin. the automatic switchover occurs when ref1 disappears. a switchover deglitch feature ensures that the pll does not receive rising edges that are far out of alignment with the newly selected reference. t here are two automatic reference switchover modes, as follows, that are set in register 0x01c: ? prefer ref1. switch from ref1 to ref2 when ref1 disappears. return to ref1 from ref2 when ref1 returns. ? stay on ref2. automatically switch to ref2 if ref1 disappears but do not switch back to ref1 if it reappears. the reference can be set back to ref1 manually at an appropriate time. in automatic mode, ref1 is monitored by ref2. if ref1 disappears (two consecutive falling edges of ref2 without an edge transition on ref1), ref1 is considered missing. on the next subsequent rising edge of ref2, ref2 is used as the reference clock to the pll. if register 0x01c[3] = 0b (default), when ref1 returns (four rising edges of ref1 without two falling edges of ref2 between the ref1 edges), the pll reference switches back to ref1. if register 0x01c[3] = 1b, the user can control when to switch back to ref1. this is done by programming the part to manual reference select mode (register 0x01c[4] = 0b) and by ensuring that the registers and/or the ref_sel pin are set to select the desired reference. automatic mode can be reactivated when ref1 is reselected. manual switchover requires that a clock must be present on the reference input being switched to or that the deglitch feature must be disabled (register 0x01c[7]). reference divider r the reference inputs are routed to the reference divider, r. r (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to register 0x011 and register 0x012. (both r = 0 and r = 1 give divide-by-1.) the output of the r divider goes to one of the pfd inputs to be compared with the vco frequency divided by the n divider. the frequency applied to the pfd must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see table 2 ). the r counter has its own reset. the r counter can be reset using the shared reset bit of the r, a, and b counters. it can also be reset by a sync operation. vcxo/vco feedback divider np, a, b, r the n divider is a combination of a prescaler (p) and two counters, a and b. the total divider value is n = ( p b ) + a where p can be 2, 4, 8, 16, or 32. prescaler the prescaler of the ad9518 allows for two modes of operation: a fixed divide (fd) mode of 1, 2, or 3, and a dual modulus (dm) mode where the prescaler divides by p and (p + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. the prescaler modes of operation are given in table 4 4 , register 0x016[2:0]. not all modes are available at all frequencies (see tabl e 2 ).
ad9518-4 rev. a | page 29 of 64 when operating the ad9518 in dual modulus mode (p//p + 1), the equation used to relate input reference frequency to vco output frequency is f vco = ( f ref / r ) ( p b + a ) = f ref n / r however, when operating the prescaler in fd mode 1, 2, or 3, the a counter is not used (a = 0) and the equation simplifies to f vco = ( f ref / r ) ( p b ) = f ref n / r when a = 0, the divide is a fixed divide of p = 2, 4, 8, 16, or 32, in which case the previous equation also applies. by using combinations of dm and fd modes, the ad9518 can achieve values of n all the way down to n = 1 and up to n = 262175. table 27 shows how a 10 mhz reference input can be locked to any integer multiple of n. note that the same value of n can be derived in different ways, as illustrated by the case of n = 12. the user can choose a fixed divide mode of p = 2 with b = 6, use the dual modulus mode of 2/3 with a = 0, b = 6, or use the dual modulus mode of 4/5 with a = 0, b = 3. a and b counters the b counter must be 3 or bypassed, and, unlike the r counter, a = 0 is actually zero. when the prescaler is in dual modulus mode, the a counter must be less than the b counter. the maximum input frequency to the a/b counter is reflected in the maximum prescaler output frequency (~300 mhz) that is specified in table 2 . this is the prescaler input frequency (vco or clk) divided by p. for example, a dual modulus mode of p = 8/9 is not allowed if the vco frequency is greater than 2400 mhz because the frequency going to the a/b counter is too high. when the ad9518 b counter is bypassed (b = 1), the a counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, p. the possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. this mode is useful only when an external vco/vcxo is used because the frequency range of the internal vco requires an overall feedback divider greater than 32. although manual reset is not normally required, the a/b counters have their own reset bit. alternatively, the a and b counters can be reset using the shared reset bit of the r, a, and b counters. note that these reset bits are not self-clearing. r, a, and b counters sync pin reset the r, a, and b counters can also be reset simultaneously through the sync pin. this function is controlled by register 0x019[7:6] (see ). the table 44 sync pin reset is disabled by default. r and n divider delays both the r and n dividers feature a programmable delay cell. these delays can be enabled to allow adjustment of the phase relationship between the pll reference clock and the vco or clk. each delay is controlled by three bits. the total delay range is about 1 ns. see register 0x019 in table 44 . table 27. using a 10 mhz reference input to generate different vco frequencies f ref (mhz) r p a b n f vco (mhz) mode comments/conditions 10 1 1 x 1 1 10 fd p = 1, b = 1 (a and b counters are bypassed). 10 1 2 x 1 2 20 fd p = 2, b = 1 (a and b counters are bypassed). 10 1 1 x 3 3 30 fd a counter is bypassed. 10 1 1 x 4 4 40 fd a counter is bypassed. 10 1 1 x 5 5 50 fd a counter is bypassed. 10 1 2 x 3 6 60 fd a counter is bypassed. 10 1 2 0 3 6 60 dm 10 1 2 1 3 7 70 dm 10 1 2 2 3 8 80 dm 10 1 2 1 4 9 90 dm 10 1 8 6 18 150 1500 dm 10 1 8 7 18 151 1510 dm 10 1 16 7 9 151 1510 dm 10 10 32 6 47 1510 1510 dm 10 1 8 0 25 200 2000 dm 10 1 16 14 16 270 2700 dm p = 8 is not allowed (2700 8 > 300 mhz). p = 32 is not allowed (a > b is not allowed). 10 10 32 22 84 2710 2710 dm p = 32, a = 22, b = 84. p = 16 is also permitted.
ad9518-4 rev. a | page 30 of 64 digital lock detect (dld) by selecting the proper output through the mux on each pin, the dld function can be made available at the ld, status, and refmon pins. the dld circuit indicates a lock when the time difference of the rising edges at the pfd inputs is less than a specified value (the lock threshold). the loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. the lock detect window timing depends on three settings: the digital lock detect window bit (register 0x018[4]), the antibacklash pulse width setting (register 0x017[1:0], see table 2 ), and the lock detect counter (register 0x018[6:5]). a lock is not indicated until there is a programmable number of consecutive pfd cycles with a time difference that is less than the lock detect threshold. the lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. for the lock detect to work properly, the period of the pfd frequency must be greater than the unlock threshold. the number of consecutive pfd cycles required for lock is programmable (register 0x018[6:5]). a nalog lock detect (ald) t he ad9518 provides an ald function that can be selected for use at the ld pin. there are two versions of ald, as follows: ? n-channel open-drain lock detect. this signal requires a pull-up resistor to the positive supply, vs. the output is normally high with short, low-going pulses. lock is indicated by the minimum duty cycle of the low-going pulses. ? p-channel open-drain lock detect. this signal requires a pull-down resistor to gnd. the output is normally low with short, high-going pulses. lock is indicated by the minimum duty cycle of the high-going pulses. the analog lock detect function requires an r-c filter to provide a logic level indicating lock/unlock. ad9518-4 ald c ld r1 v out r2 v s = 3.3 v 0 6433-067 figure 34. example of analog lock detect filter using an n-channel open-drain driver current source digital lock detect (dld) during the pll locking sequence, it is normal for the dld signal to toggle a number of times before remaining steady when the pll is completely locked and stable. there may be applications where it is desirable to have dld asserted only after the pll is solidly locked. this is made is possible by using the current source lock detect function. the current source lock detect function is set when it is selected as the output from the ld pin control (register 0x01a[5:0]). the current source lock detect provides a current of 110 a when dld is true, and it shorts to ground when dld is false. if a capacitor is connected to the ld pin, it charges at a rate that is determined by the current source during the dld true time but is discharged nearly instantly when dld is false. by monitoring the voltage at the ld pin (top of the capacitor), it is possible to get a logic high level only after the dld has been true for a sufficiently long time. any momentary dld false resets the charging. by selecting a properly sized capacitor, it is possible to delay a lock detect indication until the pll is stably locked and the lock detect does not chatter. the voltage on the capacitor can be sensed by an external comparator connected to the ld pin. however, there is an internal ld pin comparator that can be read at the refmon pin control (register 0x01b[4:0]) or the status pin control (register 0x017[7:2]) as an active high signal. it is also available as an active low signal (refmon, register 0x01b[4:0] and status, register 0x017[7:2]). the internal ld pin comparator trip point and hysteresis are listed in table 15 . ad9518-4 110a dld ld pin comparator ld refmon or status c v out 06433-068 figure 35. current source digital lock detect external vcxo/vco clock input (clk/ clk ) clk is a differential input that can be used as an input to drive the ad9518 clock distribution section. this input can receive up to 2.4 ghz. the pins are internally self-biased, and the input signal should be ac-coupled via capacitors. vs clock input stage c lk c lk 5k? 2.5k ? 2.5k ? 06433-032 5k? figure 36. clk equivalent input circuit the clk/ clk input can be used either as a distribution-only input (with the pll off), or as a feedback input for an external vco/vcxo using the internal pll when the internal vco is not used. the clk/ clk input can be used for frequencies up to 2.4 ghz.
ad9518-4 rev. a | page 31 of 64 holdover the ad9518 pll has a holdover function. holdover is implemented by putting the charge pump into a high impedance state. this is useful when the pll reference clock is lost. holdover mode allows the vco to maintain a relatively constant frequency even though there is no reference clock. without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive vco frequency shift. because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the vco tuning node causes a drift of the vco frequency. this can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate (i leak /c) of the vco control voltage. for most applications, the frequency accuracy is sufficient for 3 sec to 5 sec. both a manual holdover, using the sync pin, and an automatic holdover mode are provided. to use either function, the holdover function must be enabled (register 0x01d[0] and register 0x01d[2]). note that the vco cannot be calibrated with the holdover enabled because the holdover resets the n divider during calibration, which prevents proper calibration. disable holdover before issuing a vco calibration. manual holdover mode a manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the sync pin is asserted low. this operation is edge sensitive, not level sensitive. the charge pump enters a high impedance state immediately. to take the charge pump out of a high impedance state, take the sync pin high. the charge pump then leaves high impedance state synchronously with the next pfd rising edge from the reference clock. this prevents extraneous charge pump events from occurring during the time between sync going high and the next pfd event. this also means that the charge pump stays in a high impedance state as long as there is no reference clock present. the b-counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. when using this mode, set the channel dividers to ignore the sync pin (at least after an initial sync event). if the dividers are not set to ignore the sync pin, each time sync is taken low to put the part into holdover, the distribution outputs turn off. automatic/internal holdover mode when enabled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. the assumption is that the only reason the loop loses lock is due to the pll losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the vco frequency as close as possible to the original frequency before the reference clock disappears. a flow chart of the internal/ automatic holdover function operation is shown in figure 37 . no no no no yes yes yes yes yes pll enabled dld == low was ld pin == high when dld went low? high impedance charge pump reference edge at pfd? release charge pump high impedance dld == high loop out of lock. digital lock detect signal goes low when the loop leaves lock as determined by the phase difference at the input of the pfd. charge pump is made high impedance. pll counters continue operating normally. charge pump remains high impedance until the reference has returned. take charge pump out of high impedance. pll can now resettle. wait for dld to go high. this takes 5 to 255 cycles (programming of the dld delay counter) with the reference and feedback clocks inside the lock window at the pfd. this ensures that the holdover function waits for the pll to settle and lock before the holdover function can be retriggered. yes 06433-069 analog lock detect pin indicates lock was previously achieved. (0x01d[3] = 1: use ld pin voltage with holdover. 0x01d[3] = 0: ignore ld pin voltage, treat ld pin as always high.) figure 37. flow chart of auto matic/internal holdover mode the holdover function senses the logic level of the ld pin as a condition to enter holdover. the signal at ld can be from the dld, ald, or current source ld mode. it is possible to disable the ld comparator (register 0x01d[3]), which causes the holdover function to always sense ld as high.
ad9518-4 rev. a | page 32 of 64 if dld is used, it is possible for the dld signal to chatter some while the pll is reacquiring lock. the holdover function may retrigger, thereby preventing the holdover mode from terminating. use of the current source lock detect mode is recommended to avoid this situation (see the current source digital lock detect section). once in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. as in the external holdover mode, the b counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps to align the edges out of the r and n dividers for faster settling of the pll and to reduce frequency errors during settling. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. after leaving holdover, the loop then reacquires lock and the ld pin must charge (if register 0x01d[3] = 1) before it can re-enter holdover (cp high impedance). t he holdover function always responds to the state of the currently selected reference (register 0x01c). if the loop loses lock during a reference switchover (see the reference switchover section), holdover is triggered briefly until the next reference clock edge at the pfd. t he following registers affect the internal/automatic holdover function: ? register 0x018[6:5], lock detect counter. this changes how many consecutive pfd cycles with edges inside the lock detect window are required for the dld indicator to indicate lock. this impacts the time required before the ld pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be re-engaged. ? register 0x018[3], disable digital lock detect. this bit must be set to 0 to enable the dld circuit. internal/automatic holdover does not operate correctly without the dld function enabled. ? register 0x01a[5:0], lock detect pin output select. set to 000100b to put it in the current source lock detect mode if using the ld pin comparator. load the ld pin with a capacitor of an appropriate value. ? register 0x01d[3], ld pin comparator enable. 1 = enable; 0 = disable. when disabled, the holdover function always senses the ld pin as high. ? register 0x01d[1], external holdover control enable. ? register 0x01d[0] and register 0x01d[2], holdover function enable. if holdover is disabled, both external and internal/automatic holdover are disabled. f or example, to use automatic holdover with the following: ? automatic reference switchover, prefer ref1 ? digital lock detect: five pfd cycles, high range window ? automatic holdover using the ld pin comparator s et the following registers (in addition to the normal pll registers): ? register 0x018[6:5] = 00b; lock detect counter = five cycles ? register 0x018[4] = 0b; lock detect window = high range ? register 0x018[3] = 0b; dld normal operation ? register 0x01a[5:0] = 000100b; current source lock detect mode ? register 0x01c[4] = 1b; automatic reference switchover enabled ? register 0x01c[3] = 0b; prefer ref1 ? register 0x01c[2:1] = 11b; enable ref1 and ref2 input buffers ? register 0x01d[3] = 1b; enable ld pin comparator ? register 0x01d[2]=1b; enable the holdover function ? register 0x01d[1] = 0b; use internal/automatic holdover mode ? register 0x01d[0] = 1b; enable the holdover function frequency status monitors the ad9518 contains three frequency status monitors that are used to indicate if the pll reference (or references in the case of single-ended mode) and the vco have fallen below a threshold frequency. a diagram showing their location in the pll is shown in figure 38 . the pll reference monitors have two threshold frequencies: normal and extended (see tabl e 15 ). the reference frequency monitor thresholds are selected in register 0x01f.
ad9518-4 rev. a | page 33 of 64 programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 status status r divider vco status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) vco phase frequency detector lock detect charge pump pll reference hold 0 01 1 divide by 2, 3, 4, 5, or 6 06433-070 figure 38. reference and vco status monitors vco calibration t he ad9518 on-chip vco must be calibrated to ensure proper operation over process and temperature. the vco calibration is controlled by a calibration controller running off of a divided refin clock. the calibration requires that the pll be set up properly to lock the pll loop and that the refin clock be present. during the first initialization after a power-up or a reset of the ad9518, a vco calibration sequence is initiated by setting register 0x018[0] = 1b. this can be done as part of the initial setup before executing update registers (register 0x232[0] = 1b). subsequent to the initial setup, a vco calibration sequence is initiated by resetting register 0x018[0] = 0b, executing an update registers operation, setting register 0x018[0] = 1b, and executing another update registers operation. the readback bit (register 0x1f[6]) indicates when a vco calibration is finished by returning a logic true (that is, 1b). t he sequence of operations for the vco calibration is as follows: ? program the pll registers to the proper values for the pll loop. note that that automatic holdover mode must be disabled, and the vco divider must not be set to static. ? ensure that the input reference signal is present. ? for the initial setting of the registers after a power-up or reset, initiate vco calibration by setting register 0x018[0] = 1b. subsequently, whenever a calibration is desired, set register 0x018[0] = 0b, update registers; and then set register 0x018[0] = 1b, update registers. ? a sync operation is initiated internally, causing the outputs to go to a static state determined by normal sync function operation. ? vco calibrates to the desired setting for the requested vco frequency. ? internally, the sync signal is released, allowing outputs to continue clocking. ? pll loop is closed. ? pll locks. a sync is executed during the vco calibration; therefore, the outputs of the ad9518 are held static during the calibration, which prevents unwanted frequencies from being produced. however, at the end of a vco calibration, the outputs may resume clocking before the pll loop is completely settled. the vco calibration clock divider is set as shown in table 44 (register 0x018[2:1]). the calibration divider divides the pfd frequency (reference frequency divided by r) down to the calibration clock. the calibration occurs at the pfd frequency divided by the calibration divider setting. lower vco calibration clock frequencies result in longer times for a calibration to be completed. the vco calibration clock frequency is given by f cal_clock = f refin /( r cal_div ) where: f refin is the frequency of the refin signal. r is the value of the r divider. cal_div is the division set for the vco calibration divider (register 0x018[2:1]). the vco calibration takes 4400 calibration clock cycles. therefore, the vco calibration time in pll reference clock cycles is given by time to calibrate vco = 4400 r cal_div pll reference clock cycles table eample time to complete a vco calibration with different f refin freuencies f refin mh r divider pfd time to calibrate vco 100 1 100 mhz 88 s 10 10 1 mhz 8.8 ms 10 100 100 khz 88 ms
ad9518-4 rev. a | page 34 of 64 v co calibration must be manually initiated. this allows for flexibility in deciding what order to program registers and when to initiate a calibration, instead of having it happen every time the values of certain pll registers change. for example, this allows for the vco frequency to be changed by small amounts without having an automatic calibration occur each time; this should be done with caution and only when the user knows the vco control voltage is not going to exceed the nominal best performance limits. for example, a few 100 khz steps are fine, but a few mhz might not be. in addition, because the calibration procedure results in rapid changes in the vco frequency, the distribution section is automatically placed in sync until the calibration is finished. therefore, this temporary loss of outputs must be expected. a vco calibration should be initiated under the following conditions: ? after changing any of the pll r, p, b, and a divider settings, or after a change in the pll reference clock frequency. this, in effect, means any time a pll register or reference clock is changed such that a different vco frequency results. ? whenever system calibration is desired. the vco is designed to operate properly over extremes of temperatures even when it is first calibrated at the opposite extreme. however, a vco calibration can be initiated at any time, if desired. clock distribution a clock channel consists of a pair of outputs that share a common divider. the ad9518 has three channels, each with two lvpecl outputs, for a total of six lvpecl outputs. each channel has its own programmable divider that divides the clock frequency that is applied to its input. the channel dividers can divide by any integer from 2 to 32, or the divider can be bypassed to achieve a divide-by-one. because the internal vco frequency is above the maximum channel divider input frequency (1600 mhz), the vco divider must be used after the on-chip vco. the vco divider can be set to divide by 2, 3, 4, 5, or 6. external clock signals connected to the clk input also require the vco divider if the frequency of the signal is greater than 1600 mhz. the channel dividers allow for a selection of various duty cycles, depending on the currently set division. that is, for any specific division, d, the output of the divider can be set to high for n + 1 input clock cycles and low for m + 1 input clock cycles (where d = n + m + 2). for example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide- by-5 can be high for three divider input cycles and low for two cycles. other combinations are also possible. the channel dividers include a duty-cycle correction function that can be disabled. in contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. however, this requires that the division be set by m = n + 1. in addition, the channel dividers allow a coarse phase offset or delay to be set. depending on the division selected, the output can be delayed by up to 31 input clock cycles. the divider outputs can also be set to start high or to start low. internal vco or external clk as clock source the clock distribution of the ad9518 has two clock input sources: an internal vco or an external clock connected to the clk/ clk pins. either the internal vco or clk must be chosen as the source of the clock signal to distribute. when the internal vco is selected as the source, the vco divider must be used. when clk is selected as the source, it is not necessary to use the vco divider if the clk frequency is less than the maximum channel divider input frequency (1600 mhz); otherwise, the vco divider must be used to reduce the frequency to one that can be accepted by the channel dividers. shows how the vco, clk, and vco divider are selected. register 0x1e1[1:0] selects the channel divider source and determines whether the vco divider is used. it is not possible to select the vco without using the vco divider. table 29 table 29. selecting vco or clk as source for channel divider, and whether vco divider is used register 0x1e1 channel divider source vco divider 1 0 0 0 clk used 0 1 clk not used 1 0 vco used 1 1 not allowed not allowed clk or vco direct to lvpecl outputs it is possible to connect either the internal vco or the clk (whichever is selected as the input to the vco divider) directly to the lvpecl outputs, out0 to out5. this configuration can pass frequencies up to the maximum frequency of the vco directly to the lvpecl outputs. the lvpecl outputs may not be able to provide a full voltage swing at the highest frequencies. to connect the lvpecl outputs directly to the internal vco or clk, the vco divider must be selected as the source to the distribution section, even if no channel uses it. either the internal vco or the clk can be selected as the source for the direct-to-output routing. table 30. settings for routing vco divider input directly to lvpecl outputs register setting selection 0x1e1[1:0] = 00b clk is the source; vco divider selected 0x1e1[1:0] = 10b vco is the source; vco divider selected 0x192[1] = 1b direct to output out0, out1 0x195[1] = 1b direct to output out2, out3 0x198[1] = 1b direct to output out4, out5
ad9518-4 rev. a | page 35 of 64 clock frequency division the total frequency division is a combination of the vco divider (when used) and the channel divider. when the vco divider is used, the total division from the vco or clk to the output is the product of the vco divider (2, 3, 4, 5, 6) and the division of the channel divider. table 31 indicates how the frequency division for a channel is set. table 31. frequency division for divider 0 to divider 2 clk or vco selected vco divider channel divider direct to output frequency division clk/vco 2 to 6 1 (bypassed) yes 1 clk/vco 2 to 6 1 (bypassed) no (2 to 6) (1) clk/vco 2 to 6 2 to 32 no (2 to 6) (2 to 32) clk not used 1 (bypassed) no 1 clk not used 2 to 32 no 2 to 32 the channel dividers feeding the lvpecl output drivers contain one 2-to-32 frequency divider. this divider provides for division by 2 to 32. division by 1 is accomplished by bypassing the divider. the dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. a phase offset or delay in increments of the input clock cycle is selectable. the channel dividers operate with a signal at their inputs up to 1600 mhz. the features and settings of the dividers are selected by programming the appropriate setup and control registers (see table 42 through table 49 ). vco divider the vco divider provides frequency division between the internal vco or the external clk input and the clock distribution channel dividers. the vco divider can be set to divide by 2, 3, 4, 5, or 6 (see table 47 , register 0x1e0[2:0]). channel dividerslvpecl outputs each pair of lvpecl outputs is driven by a channel divider. there are three channel dividers (0, 1, and 2) driving a total of six lvpecl outputs (out0 to out5). table 3 2 gives the register locations used for setting the division and other functions of these dividers. the division is set by the values of m and n. the divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. the duty-cycle correction can be enabled or disabled according to the setting of the dccoff bits. table 32. setting d x for divider 0, divider 1, and divider 2 1 divider low cycles m high cycles n bypass dccoff 0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0] 1 note that the value stored in the register = # of cycles minus 1. channel frequency division (0, 1, and 2) for each channel (where the channel number is x: 0, 1, or 2), the frequency division, d x , is set by the values of m and n (four bits each, representing decimal 0 to decimal 15), where number of low cycles = m + 1 number of high cycles = n + 1 the cycles are cycles of the clock signal currently routed to the input of the channel dividers (vco divider out or clk). when a divider is bypassed, d x = 1. otherwise, d x = (n + 1) + (m + 1) = n + m + 2. this allows each channel divider to divide by any integer from 2 to 32. d uty cycle and duty-cycle correction (0, 1, and 2) t he duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: ? what are the m and n values for the channel? ? is the dcc enabled? ? is the vco divider used? ? what is the clk input duty cycle? (the internal vco has a 50% duty cycle.) t he dcc function is enabled by default for each channel divider. however, the dcc function can be disabled individually for each channel divider by setting the dccoff bit for that channel. c ertain m and n values for a channel divider result in a non-50% duty cycle. a non-50% duty cycle can also result with an even division, if m n. the duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. duty-cycle correction requires the following channel divider conditions: ? an even division must be set as m = n. ? an odd division must be set as m = n + 1. when not bypassed or corrected by the dcc function, the duty cycle of each channel divider output is the numerical value of (n + 1)/(n + m + 2), expressed as a percentage (%). the duty cycle at the output of the channel divider for various configurations is shown in table 33 to table 35 . table 33. duty cycle with vco divider, input duty cycle is 50% vco divider d x output duty cycle n + m + 2 dccoff = 1 dccoff = 0 even 1 (divider bypassed) 50% 50% odd = 3 1 (divider bypassed) 33.3% 50% odd = 5 1 (divider bypassed) 40% 50% even, odd even (n + 1)/ (n + m + 2) 50%; requires m = n even, odd odd (n + 1)/ (n + m + 2) 50%; requires m = n + 1
ad9518-4 rev. a | page 36 of 64 table 34. duty cycle with vco divider, input duty cycle is x% vco divider d x output duty cycle n + m + 2 dccoff = 1 dccoff = 0 even 1 (divider bypassed) 50% 50% odd = 3 1 (divider bypassed) 33.3% (1 + x%)/3 odd = 5 1 (divider bypassed) 40% (2 + x%)/5 even even (n + 1)/ (n + m + 2) 50%, requires m = n odd (n + 1)/ (n + m + 2) 50%, requires m = n + 1 odd = 3 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 3 odd (n + 1)/ (n + m + 2) (3n + 4 + x%)/(6n + 9), requires m = n + 1 odd = 5 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 5 odd (n + 1)/ (n + m + 2) (5n + 7 + x%)/(10n + 15), requires m = n + 1 table 35. channel divider output duty cycle when the vco divider is not used input clock duty cycle d x output duty cycle n + m + 2 dccoff = 1 dccoff = 0 any 1 1 (divider bypassed) same as input duty cycle any even (n + 1)/ (m + n + 2) 50%, requires m = n 50% odd (n + 1)/ (m + n + 2) 50%, requires m = n + 1 x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3), requires m = n + 1 the internal vco has a duty cycle of 50%. therefore, when the vco is connected directly to the output, the duty cycle is 50%. if the clk input is routed directly to the output, the duty cycle of the output is the same as the clk input. phase offset or coarse time delay (0, 1, and 2) each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see table 36 ). these settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. this delay is with respect to a nondelayed output (that is, with a phase offset of zero). the amount of the delay is set by five bits loaded into the phase offset (po) register plus the start high (sh) bit for each channel divider. when the start high bit is set, the delay is also affected by the number of low cycles (m) programmed for the divider. the sync function must be used to make phase offsets effective (see the synchronizing the outputssync function section). table 36. setting phase offset and division for divider 0, divider 1, and divider 2 divider start high (sh) phase offset (po) low cycles m high cycles n 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] let t = delay (in seconds). c = delay (in cycles of clock signal at input to d x ). t x = period of the clock signal at the input of the divider, d x (in seconds). = 16 sh[4] + 8 po[3] + 4 po[2] + 2 po[1] + 1 po[0] the channel divide-by is set as n = high cycles and m = low cycles. case 1 for 15, t = t x c = t/t x = case 2 for 16, t = ( ? 16 + m + 1) t x c = t/t x by giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. figure 39 shows the results of setting such a coarse offset between outputs. 0123456789101112131415 tx c h a n n e l d i v i d e r o u t p u t s d i v = 4 , d u t y = 5 0 % divider 0 divider 1 divider 2 channel divider input sh = 0 po = 0 sh = 0 po = 1 sh = 0 po = 2 1 tx 2 tx 06433-071 figure 39. effect of coarse phase offset (or delay) synchronizing the outputssync function the ad9518 clock outputs can be synchronized to each other. outputs can be individually excluded from synchronization. synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied. this allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs.
ad9518-4 synchronization of the outputs is executed in several ways. ? the sync pin is forced low and then released (manual sync). ? by setting and then resetting any one of the following three bits: the soft sync bit (register 0x230[0]), the soft reset bit (register 0x000[2] [mirrored]), and the power down distribution reference bit (register 0x230[1]). ? synchronization of the outputs can be executed as part of the chip power-up sequence. ? the reset pin is forced low and then released (chip reset). ? the pd pin is forced low, then released (chip power-down). ? when a vco calibration is completed, an internal sync signal is automatically asserted at the beginning and released upon the completion of a vco calibration. the most common way to execute the sync function is to use the sync pin to do a manual synchronization of the outputs. this requires a low-going signal on the sync pin, which is held low and then released when synchronization is desired. the timing of the sync operation is shown in (using the vco divider) and (vco divider not used). there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the sync signal with respect to the clock edges inside the ad9518. the delay from the figure 40 figure 41 sync rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the vco divider input (see ), or one cycle of the clk input (see ), depending on whether the vco divider is used. cycles are counted from the rising edge of the signal. figure 40 figure 41 another common way to execute the sync function is by setting and resetting the soft sync bit at register 0x230[0] (see table 43 through table 4 9 for details). both setting and resetting of the soft sync bit require an update all registers (register 0x232[0] = 1) operation to take effect. rev. a | page 37 of 64 1234567 8 910 input to vco divider input to channel divider output of channel divider s ync pin 1 11 12 13 14 14 to 15 cycles at channel divider input + 1 cycle at vco divider input channel divider output static channel divide r output clocking channel divide r output clocking 06 433-073 figure 40. sync timing when vco divider is usedclk or vco is input input to clk iinput to channel divider output of channel divider sync pin 14 to 15 cycles at channel divider input + 1 cycle at clk input 1234567 8 910 11 12 13 14 1 channel divider output static channel divide r output clocking channel divider output clocking 0 6433 -074 figure 41. sync timing when vco di vider is not usedclk input only
ad9518-4 rev. a | page 38 of 64 a sync operation brings all outputs that have not been excluded (by the nosync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. the preset condition takes into account the settings in each of the channels start high bit and its phase offset. these settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation. between outputs and after synchronization, this allows for the setting of phase offsets. the ad9518 outputs are in pairs, sharing a channel divider per pair. the synchronization conditions apply to both outputs of a pair. each channel (a divider and its outputs) can be excluded from any sync operation by setting the nosync bit of the channel. channels that are set to ignore sync (excluded channels) do not set their outputs static during a sync operation, and their outputs are not synchronized with those of the nonexcluded channels. lvpecl outputsout0 to out3 the lvpecl differential voltage (v od ) is selectable from ~400 mv to ~960 mv (see register 0x0f0[3:2] to register 0x0f5[3:2]). the lvpecl outputs have dedicated pins for power supply (vs_lvpecl), allowing a separate power supply to be used. v s_lvpecl can be from 2.5 v to 3.3 v. the lvpecl output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. each lvpecl output can be powered down or powered up, as needed. because of the architecture of the lvpecl output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. for this reason, the lvpecl outputs have several power-down modes. this includes a safe power-down mode that continues to protect the output devices while powered down, although it consumes somewhat more power than a total power-down. if the lvpecl output pins are terminated, it is best to select the safe power-down mode. if the pins are not connected (unused), it is acceptable to use the total power-down mode. gnd 3.3 v out out 06433-033 figure 42. lvpecl output simplified equivalent circuit reset modes the ad9518 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. power-on resetstart-up conditions when v s is applied a power-on reset (por) is issued when the v s power supply is turned on. this initializes the chip to the power-on conditions that are determined by the default register settings. these are indicated in the default value (hex) column of table 42 . at power-on, the ad9518 also executes a sync operation, which brings the outputs into phase alignment according to the default settings. asynchronous reset via the reset pin an asynchronous hard reset is executed by momentarily pulling reset low. a reset restores the chip registers to the default settings. soft reset via register 0x 0 00[2] a soft reset is executed by writing register 0x000[2] and register 0x000[5] = 1b. this bit is not self-clearing; it must be cleared by writing register 0x000[2] and register 0x000[5] = 0b to reset it and complete the soft reset operation. a soft reset restores the default values to the internal registers. the soft reset bit does not require an update registers command (register 0x232) to be issued. power-down modes chip power-down via pd the ad9518 can be put into a power-down condition by pulling the pd pin low. power-down turns off most of the functions and currents inside the ad9518. the chip remains in this power-down state until pd is brought back to logic high. when the ad9518 wakes up, it returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the pd pin is held low. the pd power-down shuts down the currents on the chip, except the bias current necessary to maintain the lvpecl outputs in a safe shutdown mode. this is needed to protect the lvpecl output circuitry from damage that could be caused by certain termination and load configurations when tristated. because this is not a complete power-down, it can be called sleep mode. w hen the ad9518 is in a pd power-down, the chip is in the following state: ? the pll is off (asynchronous power-down). ? the vco is off. ? the clk input buffer is off. ? all dividers are off. ? all lvpecl outputs are in safe off mode. ? the serial control port is active, and the chip responds to commands.
ad9518-4 rev. a | page 39 of 64 if the ad9518 clock outputs must be synchronized to each other, a sync is required upon exiting power-down (see the synchronizing the outputssync function section). a vco calibration is not required when exiting power-down. pll power-down the pll section of the ad9518 can be selectively powered down. there are three pll operating modes set by register 0x010[1:0], as shown in table 44 . in asynchronous power-down mode, the device powers down as soon as the registers are updated. in synchronous power-down mode, the pll power-down is gated by the charge pump to prevent unwanted frequency jumps. the device goes into power-down on the occurrence of the next charge pump event after the registers are updated. distribution power-down the distribution section can be powered down by writing register 0x230[1] = 1b. this turns off the bias to the distribution section. if the lvpecl power-down mode is normal operation (00b), it is possible for a low impedance load on that lvpecl output to draw significant current during this power-down. if the lvpecl power-down mode is set to 11b, the lvpecl output is not protected from reverse bias and may be damaged under certain termination conditions. individual clock output power-down any of the clock distribution outputs can be powered down individually by writing to the appropriate registers. the register map details the individual power-down settings for each output. the lvpecl outputs have multiple power-down modes (see table 45 ), which give some flexibility in dealing with the various output termination conditions. when the mode is set to 10b, the lvpecl output is protected from reverse bias to 2 vbe + 1 v. if the mode is set to 11b, the lvpecl output is not protected from reverse bias and can be damaged under certain termination conditions. this setting also affects the operation when the distribution block is powered down with register 0x230[1] = 1b (see the distribution power-down section). individual circuit block power-down other ad9518 circuit blocks (such as clk, ref1, and ref2) can be powered down individually. this gives flexibility in configuring the part for power savings whenever certain chip functions are not needed.
ad9518-4 rev. a | page 40 of 64 serial control port the ad9518 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. the ad9518 serial control port is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr? protocols. the serial control port allows read/write access to all registers that configure the ad9518. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9518 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio/sdo). by default, the ad9518 is in bidirectional mode, long instruction (long instruction is the only instruction mode supported). serial control port pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled down by a 30 k resistor to ground. sdio (serial data input/output) is a dual-purpose pin that acts as either an input only (unidirectional mode) or as both an input and an output (bidirectional mode). the ad9518 defaults to the bidirectional i/o mode (register 0x000[0] = 0). sdo (serial data out) is used only in the unidirectional i/o mode (register 0x000[0] = 1) as a separate output pin for reading back data. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 30 k resistor to vs. ad9518-4 serial control port sclk 13 cs 14 sdo 15 sdio 16 0 6433-0 36 figure 43. serial control port general operation of serial control port a write or a read operation to the ad9518 is initiated by pulling cs low. cs stalled high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see ). in these modes, table 37 cs can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfers or by returning cs low for at least one complete sclk cycle (but less than eight sclk cycles). raising cs on a nonbyte boundary terminates the serial transfer and flushes the buffer. in streaming mode (see table 37 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending the stream mode. communication cycleinstruction plus data there are two parts to a communication cycle with the ad9518. the first part writes a 16-bit instruction word into the ad9518, coincident with the first 16 sclk rising edges. the instruction word provides the ad9518 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the ad9518. data bits are registered on the rising edge of sclk. the length of the transfer (1, 2, 3 bytes or streaming mode) is indicated by two bits ([w1:w0]) in the instruction byte. when the transfer is 1, 2, or 3 bytes, but not streaming, cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when cs is lowered. raising cs on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or blank registers, and it does not matter what data is written to blank registers. because data is written into a serial control port buffer area, not directly into the actual control registers of the ad9518, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the ad9518, thereby causing them to become active. the update registers operation consists of setting regi ster 0x232[0] = 1b (this bit is self-clearing). any number of bytes of data can be changed before executing an update registers. the update registers simultaneously actuates all register changes that have been written to the buffer since any previous update.
ad9518-4 rev. a | page 41 of 64 read if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3 as determined by [w1:w0]. if n = 4, the read operation is in streaming mode, continuing until cs is raised. streaming mode does not skip over reserved or blank registers. the readback data is valid on the falling edge of sclk. the default mode of the ad9518 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the ad9518 to unidirectional mode via the sdo active bit, register 0x000[0] = 1. in unid irectional mode, the readback data appears on the sdo pin. a readback request reads the data that is in the serial control port buffer area, or the data that is in the active registers (see figure 44 ). readback of the buffer or active registers is controlled by register 0x004[0]. the ad9518 supports only the long instruction mode; therefore, register 0x000[4:3] must be set to 11b. long instruction mode is the default at power-up or reset. the ad9518 uses register address 0x000 to register address 0x232. sclk sdio sdo cs serial control port bu write register 0x232 = 0x01 to udate registers ffer registers update registers ac tive registers 06433-037 figure 44. relationship between seri al control port buffer registers and active registers of the ad9518 the instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, [w1:w0], indicate the length of the transfer in bytes. the final 13 bits are the address ([a12:a0]) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes of data indicated by bits[w1:w0] (see table 37 ). table 37. byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode the 13 bits found in [a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. only bits[a9:a0] are needed to cover the range of the 0x232 registers used by the ad9518. bits[a12:a10] must always be 0b. for multibyte transfers, this address is the starting byte address. in msb first mode, subsequent bytes decrement the address. msb/lsb first transfers the ad9518 instruction word and byte data can be msb first or lsb first. any data written to register 0x000 must be mirrored; the upper four bits (bits[7:4]) must mirror the lower four bits (bits[3:0]). this makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, see the default setting for this register: 0x18, which mirrors bit 4 and bit 3. this sets the long instruction mode (which is the default and is the only mode supported). the default for the ad9518 is msb first. when lsb first is set by register 0x000[1] and register 0x000[6], it takes effect immediately because it affects only the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from the high address to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the internal byte address generator of the serial control port increments for each byte of the multibyte transfer cycle. the ad9518 serial control port register address decrements from the register address just written toward 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward 0x232 for multibyte i/o operations. streaming mode always terminates when it hits address 0x232. note that unused addresses are not skipped during multibyte i/o operations. table 38. streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x230, 0x231, 0x232, stop msb first decrement 0x001, 0x000, 0x232, stop
ad9518-4 rev. a | page 42 of 64 table 39. serial control port, 16-bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 = 0 a11 = 0 a10 = 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 6433 -038 cs sclk sdio sdo figure 45. serial control port writemsb fi rst, 16-bit instruct ion, two bytes data register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don?t care don?t care don?t care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 do ca n?t re 06433-039 t s don?t care don?t care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don?t care don?t care figure 46. serial control port readmsb fi rst, 16-bit instruction, four bytes data t ds t dh t high t low t c t clk cs sclk sdio r/w 06433-040 cs sclk sdio figure 47. serial control port writemsb firs t, 16-bit instruction, timing measurements data bit n ? 1 data bit n sdo t dv -041 06433 figure 48. serial control port timing diagramread cs sclk don't care don't care sdio don't care don't care a0 16-bit instruction header register (n) data register (n + 1) data a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 6433-042 figure 49. serial control port writelsb fi rst, 16-bit instruction, two bytes data
ad9518-4 rev. a | page 43 of 64 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 06433-043 figure 50. serial control port timing diagramwrite table 40. serial control port timing parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock setup time between cs falling edge and sclk rising edge (start of communication cycle) t s setup time between sclk rising edge and cs rising edge (end of communication cycle) t c t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 48 )
ad9518-4 rev. a | page 44 of 64 thermal performance table 41. thermal parameters for the 48-lead lfcsp symbol thermal characteristic using a jedec jesd51-7 plus jedec jesd51-5 2s2p test board value (c/w) ja junction-to-ambient thermal resistance, natural convection per jedec jesd51-2 (still air) 24.7 jma junction-to-ambient thermal resistance, 1.0 m/sec airflow per jedec jesd51-6 (moving air) 21.6 jma junction-to-ambient thermal resistance, 2.5 m/sec airflow per jedec jesd51-6 (moving air) 19.4 jb junction-to-board thermal resistance, natural convection per jedec jesd51-8 (still air) 12.9 jb junction-to-board characterization parameter, na tural convection per jedec jesd51-6 (still air) and jedec jesd51-8 11.9 jb junction-to-board characterization parameter, 1.0 m/sec airflow per jedec jesd51-6 (moving air) and jedec jesd51-8 11.8 jb junction-to-board characterization parameter, 2.5 m/sec airflow per jedec jesd51-6 (moving air) and jedec jesd51-8 11.6 jc junction-to-case thermal resistance (die-to-heat sink) per mil-std-883, method 1012.1 1.3 jt junction-to-top-of-package characterization parameter, natural convection per jedec jesd51-2 (still air) 0.5 the ad9518 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the user at the top center of the package. jt is the value from table 41 . pd is the power dissipation of the device. va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j in the following equation: t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations.
ad9518-4 rev. a | page 45 of 64 control registers control register map overview table 42. control register map overview reg. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) serial port configuration 0x000 serial port configuration sdo active lsb first soft reset long instruction long instruction soft reset lsb first sdo active 0x18 0x001 blank 0x002 reserved 0x003 part id part id (read only) 0xe3 0x004 readback control blank read back active registers 0x00 pll 0x010 pfd and charge pump pfd polarity charge pump current charge pu mp mode pll power-down 0x7d 0x011 r counter 14-bit r divi der, bits[7:0] (lsb) 0x01 0x012 blank 14-bit r divide r, bits[13:8] (msb) 0x00 0x013 a counter blank 6-bit a counter 0x00 0x014 b counter 13-bit b counter, bits[7:0] (lsb) 0x03 0x015 blank 13-bit b counter, bits[12:8] (msb) 0x00 0x016 pll control 1 set cp pin to v cp /2 reset r counter reset a and b counters reset all counters b counter bypass prescaler p 0x06 0x017 pll control 2 status pin control antibacklash pulse width 0x00 0x018 pll control 3 reserved lock detect counter digital lock detect window disable digital lock detect vco calibration divider vco cal now 0x06 0x019 pll control 4 r, a, b counters sync pin reset r path delay n path delay 0x00 0x01a pll control 5 reserved reference frequency monitor threshold ld pin control 0x00 0x01b pll control 6 vco frequency monitor ref2 ( refin ) frequency monitor ref1 (refin) frequency monitor refmon pin control 0x00 0x01c pll control 7 disable switchover deglitch select ref2 use ref_sel pin automatic reference switchover stay on ref2 ref2 power-on ref1 power-on differential reference 0x00 0x01d pll control 8 reserved pll status register disable ld pin comparator enable holdover enable external holdover control holdover enable 0x00 0x01e pll control 9 reserved 0x00 0x01f pll readback reserved vco cal finished holdover active ref2 selected vco frequency > threshold ref2 frequency > threshold ref1 frequency > threshold digital lock detect n/a 0x020 to 0x04f blank 0x0a0 to 0x0ab reserved 0x0ac to 0x0ef blank
ad9518-4 rev. a | page 46 of 64 reg. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) lvpecl outputs 0x0f0 out0 blank out0 invert out0 lvpecl differential voltage out0 power-down 0x08 0x0f1 out1 blank out1 invert out1 lvpecl differential voltage out1 power-down 0x0a 0x0f2 out2 blank out2 invert out2 lvpecl differential voltage out2 power-down 0x08 0x0f3 out3 blank out3 invert out3 lvpecl differential voltage out3 power-down 0x0a 0x0f4 out4 blank out4 invert out4 lvpecl differential voltage out4 power-down 0x08 0x0f5 out5 blank out5 invert out5 lvpecl differential voltage out5 power-down 0x0a 0x0f6 to 0x13f blank 0x140 to 0x143 reserved 0x144 to 0x18f blank lvpecl channel dividers 0x190 divider 0 (pecl) divider 0 low cycles divi der 0 high cycles 0x00 0x191 divider 0 bypass divider 0 nosync divider 0 force high divider 0 start high divider 0 phase offset 0x80 0x192 blank reserved divider 0 direct to output divider 0 dccoff 0x00 0x193 divider 1 (pecl) divider 1 low cycles divi der 1 high cycles 0xbb 0x194 divider 1 bypass divider 1 nosync divider 1 force high divider 1 start high divider 1 phase offset 0x00 0x195 blank reserved divider 1 direct to output divider 1 dccoff 0x00 0x196 divider 2 (pecl) divider 2 low cycles divi der 2 high cycles 0x00 0x197 divider 2 bypass divider 2 nosync divider 2 force high divider 2 start high divider 2 phase offset 0x00 0x198 blank reserved divider 2 direct to output divider 2 dccoff 0x00 0x199 to 0x1a3 reserved 0x1a4 to 0x1df blank vco divider and clk input 0x1e0 vco divider blank reserved vco divider 0x02 0x1e1 input clks reserved power down clock input section power down vco clock interface power down vco and clk select vco or clk bypass vco divider 0x00 0x1e2 to 0x22a blank
ad9518-4 rev. a | page 47 of 64 reg. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) system 0x230 power-down and sync reserved power down sync power down distribution reference soft sync 0x00 0x231 blank reserved 0x00 update all registers 0x232 update all registers blank update all registers (self-clearing bit) 0x00 control register map descriptions table 43 through table 49 provide a detailed description of each of the control register functions. the registers are listed by hexadecimal address. a range of bits (for example, from bit 5 through bit 2) is indicated using a colon and brackets, as follows: [5:2]. table 43. serial port configuration and part id reg. addr (hex) bits name description 0x000 [7:4] mirrored, bits[3:0] bits[7:4] should always mirror bits[3:0] so that it does not matter whether the part is in msb or lsb first mode (see bit 1, register 0x000). the user should set the bits as follows: bit 7 = bit 0. bit 6 = bit 1. bit 5 = bit 2. bit 4 = bit 3. 3 long instruction short/long instruction mode. this part uses lo ng instruction mode only, so this bit should always be set to 1. 0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). 2 soft reset soft reset. 1: soft reset; restores default values to internal registers. not self-clearing. must be cleared to 0 to complete reset operation. 1 lsb first msb or lsb data orientation. 0: data-oriented msb first; addressing decrements (default). 1: data-oriented lsb first; addressing increments. 0 sdo active selects unidirectional or bidirectional data transfer mode. 0: sdio pin used for write and read; sdo set to high impedance; bidirectional mode (default). 1: sdo used for read, sdio used for write; unidirectional mode. 0x003 [7:0] part id (read only) uniquely identifies the dash version (-0 through -4) of the ad9518. ad9518-0: 0x21. ad9518-1: 0x61. ad9518-2: 0xa1. ad9518-3: 0x63. ad9518-4: 0xe3. 0x004 0 read back active registers selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers.
ad9518-4 rev. a | page 48 of 64 table 44. pll reg. addr. (hex) bits name description 0x010 7 pfd polarity sets the pfd polarity. negative polarity is for use (if needed) with external vco/vcxo only. the on-chip v co requires positive polarity; bit 7 = 0. 0: positive; higher control voltag e produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. [6:4] cp current charge pump current (with cprset = 5.1 k). 6 5 4 i cp (ma) 0 0 0 0.6. 0 0 1 1.2. 0 1 0 1.8. 0 1 1 2.4. 1 0 0 3.0. 1 0 1 3.6. 1 1 0 4.2. 1 1 1 4.8 (default). [3:2] cp mode charge pump operating mode. 3 2 charge pump mode 0 0 high impedance state. 0 1 force source current (pump up). 1 0 force sink current (pump down). 1 1 normal operation (default). [1:0] pll power- pll operating mode. down 1 0 mode 0 0 normal operation. 0 1 asynchronous power-down (default). 1 0 normal operation. 1 1 synchronous power-down. 0x011 [7:0] 14-bit r divider, bits[7:0] (lsb) r divider lsbslower eight bits (default = 0x01). 0x012 [5:0] 14-bit r divider, bits[13:8] (msb) r divider msbsupper six bits (default = 0x00). 0x013 [5:0] 6-bit a counter a counter (part of n divider) (default = 0x00). 0x014 [7:0] 13-bit b counter, bits[7:0] (lsb) b counter (part of n divider)lower eight bits (default = 0x03). 0x015 [4:0] 13-bit b counter, bits[12:8] (msb) b counter (part of n divider)upper five bits (default = 0x00). 0x016 7 set cp pin to v cp /2 sets the cp pin to one-half of the v cp supply voltage. 0: cp normal operation (default). 1: cp pin set to v cp /2. 6 reset r counter resets r counter (r divider). 0: normal (default). 1: holds the r counter in reset. 5 reset a, b counters resets a and b counters (part of n divider). 0: normal (default). 1: holds the a and b counters in reset. 4 reset all counters rese ts r, a, and b counters. 0: normal (default). 1: holds the r, a, and b counters in reset. 3 b counter b counter bypass. this is valid on ly when operating the prescaler in fd mode. bypass 0: normal (default). 1: b counter is set to divide-by-1. this allows the prescaler setting to determine the divide for the n divider.
ad9518-4 rev. a | page 49 of 64 reg. addr. (hex) bits name description 0x016 [2:0] prescaler p prescaler: dm = dual modulus and fd = fixed divide. 2 1 0 mode prescaler 0 0 0 fd divide-by-1. 0 0 1 fd divide-by-2. 0 1 0 dm divide-by-2 (2/3 mode). 0 1 1 dm divide-by-4 (4/5 mode). 1 0 0 dm divide-by-8 (8/9 mode). 1 0 1 dm divide-by-16 (16/17 mode). 1 1 0 dm divide-by-32 (32/33 mode) (default). 1 1 1 fd divide-by-3. 0x017 [7:2] status pin selects the signal that is connected to the status pin. control 7 6 5 4 3 2 level or dynamic signal signal at status pin 0 0 0 0 0 0 lvl ground (dc) (default). 0 0 0 0 0 1 dyn n divider output (after the delay). 0 0 0 0 1 0 dyn r divider output (after the delay). 0 0 0 0 1 1 dyn a divider output. 0 0 0 1 0 0 dyn prescaler output. 0 0 0 1 0 1 dyn pfd up pulse. 0 0 0 1 1 0 dyn pfd down pulse. 0 x x x x x lvl ground (dc); for all other cases of 0xxxxx not specified above. the selections that follow are the same as refmon. 1 0 0 0 0 0 lvl ground (dc). 1 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 0 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 lvl status of unselected re ference (not available in differential mode); active high. 1 0 0 1 1 1 lvl status ref1 frequency; active high. 1 0 1 0 0 0 lvl status ref2 frequency; active high. 1 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 1 0 1 0 1 1 lvl status of vco frequency; active high. 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 1 0 1 1 0 1 lvl digital lock detect (dld); active high. 1 0 1 1 1 0 lvl holdover active; active high. 1 0 1 1 1 1 lvl ld pin comparator output; active high. 1 1 0 0 0 0 lvl vs (pll supply). 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode). 1 1 0 1 0 1 lvl status of selected referenc e (status of differential reference); active low. 1 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 lvl status of ref1 frequency; active low. 1 1 1 0 0 0 lvl status of ref2 frequency; active low. 1 1 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) . 1 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 1 0 1 1 lvl status of vco frequency; active low. 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 1 0 1 lvl digital lock detect (dld); active low. 1 1 1 1 1 0 lvl holdover active; active low. 1 1 1 1 1 1 lvl ld pin comparator output; active low.
ad9518-4 rev. a | page 50 of 64 reg. addr. (hex) bits name description 0x017 [1:0] antibacklash 1 0 antibacklash pulse width (ns) pulse width 0 0 2.9 (default). 0 1 1.3. 1 0 6.0. 1 1 2.9. 0x018 [6:5] lock detect counter required consecutive number of pfd cycles with edges insi de lock detect window before the dld indicates a locked condition. 6 5 pfd cycles to determine lock 0 0 5 (default). 0 1 16. 1 0 64. 1 1 255. 4 digital lock detect window if the time difference of the rising edges at the inputs to the pfd is less than the lock detect window time, the digital lock detect flag is set. the flag remains set until the time difference is greater than the loss-of-lock threshold. 0: high range (default). 1: low range. 3 disable digital digital lock detect operation. lock detect 0: normal lock detect operation (default). 1: disables lock detect. [2:1] vco cal vco calibration divider. divider used to gene rate the vco calibration clock from the pll reference clock. divider 2 1 vco calibration clock divider 0 0 2. 0 1 4. 1 0 8. 1 1 16 (default). 0 vco cal now bit used to initiate the vco calibration. this bit must be toggled from 0 to 1 in the active registers. to initi ate calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not zero already), followed by an update bit (register 0x232, bit 0); and third, program to 1, followed by another update bit (register 0x232, bit 0). 0x019 [7:6] r, a, b counters 7 6 action sync pin reset 0 0 does nothing on sync (default). 0 1 asynchronous reset. 1 0 synchronous reset. 1 1 does nothing on sync . [5:3] r path delay r path delay (default = 0x00) (see table 2 ). [2:0] n path delay n path delay (default = 0x00) (see table 2 ).
ad9518-4 rev. a | page 51 of 64 reg. addr. (hex) bits name description 0x01a 6 reference frequency monitor sets the reference (ref1/ref2) frequency monitors detect ion threshold frequency. this does not affect the vco frequency monitors detection threshold (see table 15 , ref1, ref2, and vco frequency status monitor). threshold 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. [5:0] ld pin control selects the signal that is connected to the ld pin. 5 4 3 2 1 0 level or dynamic signal signal at ld pin 0 0 0 0 0 0 lvl digital lock detect (high = lock, low = unlock) (default). 0 0 0 0 0 1 dyn p-channel, open-dra in lock detect (analog lock detect). 0 0 0 0 1 0 dyn n-channel, open-dra in lock detect (analog lock detect). 0 0 0 0 1 1 hiz high-z ld pin. 0 0 0 1 0 0 cur current source lock detect (110 a when dld is true). 0 x x x x x lvl ground (dc); for all other cases of 0xxxxx not specified above. the selections that follow are the same as refmon. 1 0 0 0 0 0 lvl ground (dc). 1 0 0 0 0 1 dyn ref1 clock (different ial reference when in differential mode). 1 0 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 0 0 0 1 1 dyn selected reference to p ll (differential referenc e when in differential mode). 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 0 0 1 0 1 lvl status of selected refere nce (status of differential reference); active high. 1 0 0 1 1 0 lvl status of unselected re ference (not available in differential mode); active high. 1 0 0 1 1 1 lvl status ref1 frequency; active high. 1 0 1 0 0 0 lvl status ref2 frequency; active high. 1 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 1 0 1 0 1 1 lvl status of vco frequency (active high). 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 1 0 1 1 0 1 lvl digital lock detect (dld); active high. 1 0 1 1 1 0 lvl holdover active; active high. 1 0 1 1 1 1 lvl not available. do not use. 1 1 0 0 0 0 lvl vs (pll supply). 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 1 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 1 0 1 0 1 lvl status of selected refere nce (status of differential reference); active low. 1 1 0 1 1 0 lvl status of unselected re ference (not available in differential mode); active low. 1 1 0 1 1 1 lvl status of ref1 frequency; active low. 1 1 1 0 0 0 lvl status of ref2 frequency; active low. 1 1 1 0 0 1 lvl (status of ref1 frequency) an d (status of ref2 frequency) . 1 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 1 0 1 1 lvl status of vco frequency; active low. 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 1 0 1 lvl digital lock detect (dld); active low. 1 1 1 1 1 0 lvl holdover active; active low. 1 1 1 1 1 1 lvl not available. do not use.
ad9518-4 rev. a | page 52 of 64 reg. addr. (hex) bits name description 0x01b 7 vco enables or disables vco frequency monitor. frequency monitor 0: disables vco frequency monitor (default). 1: enables vco frequency monitor. 6 ref2 ( refin ) enables or disables ref2 frequency monitor. frequency monitor 0: disables ref2 frequency monitor (default). 1: enables ref2 frequency monitor. 5 ref1 (refin) frequency monitor ref1 (refin) frequency monitor enable; this is for both ref1 (single-ended) and refin (differential) inputs (as selected by differential reference mode). 0: disables ref1 (refin) frequency monitor (default). 1: enables ref1 (refin) frequency monitor. [4:0] refmon pin selects the signal th at is connected to the refmon pin. control 4 3 2 1 0 level or dynamic signal signal at refmon pin 0 0 0 0 0 lvl ground (dc) (default). 0 0 0 0 1 dyn ref1 clock (differentia l reference when in differential mode). 0 0 0 1 0 dyn ref2 clock (not available in differential mode). 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 0 0 1 1 0 lvl status of unselected referenc e (not available in differential mode); active high. 0 0 1 1 1 lvl status ref1 frequency; active high. 0 1 0 0 0 lvl status ref2 frequency; active high. 0 1 0 0 1 lvl (status ref1 freq uency) and (status ref2 frequency). 0 1 0 1 0 lvl (dld) and (status of se lected reference) and (status of vco). 0 1 0 1 1 lvl status of vco frequency; active high. 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 0 1 1 0 1 lvl digital lock detect (dld); active low. 0 1 1 1 0 lvl holdover active; active high. 0 1 1 1 1 lvl ld pin comparator output; active high. 1 0 0 0 0 lvl vs (pll supply). 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 0 1 1 0 lvl status of unse lected reference (not available in differential mode); active low. 1 0 1 1 1 lvl status of ref1 frequency; active low. 1 1 0 0 0 lvl status of ref2 frequency; active low. 1 1 0 0 1 lvl (status of ref1 frequency) an d (status of ref2 frequency) . 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 0 1 1 lvl status of vco frequency; active low. 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 0 1 lvl digital lock detect (dld); active low. 1 1 1 1 0 lvl holdover active; active low. 1 1 1 1 1 lvl ld pin comparator output; active low.
ad9518-4 rev. a | page 53 of 64 reg. addr. (hex) bits name description 0x01c 7 disable disables or enables the switchover deglitch circuit. switchover 0: enables switchover deglitch circuit (default). deglitch 1: disables switchover deglitch circuit. 6 select ref2 if register 0x01c, bit 5 = 0, select reference for pll. 0: selects ref1 (default). 1: selects ref2. 5 use ref_sel pin if register 0x01c, bit 4 = 0 (manual), sets method of pll reference selection. 0: uses register 0x01c, bit 6 (default). 1: uses ref_sel pin. 4 automatic automatic or manual reference switchover. single-ended reference mode must be selected by register 0x01c, bit 0 = 0. reference 0: manual reference switchover (default). switchover 1: automatic reference switchover. 3 stay on ref2 stays on ref2 after switchover. 0: returns to ref1 automatically when ref1 status is good again (default). 1: stays on ref2 after switchover. does not automatically return to ref1. 2 ref2 power-on when automatic reference switchov er is disabled, this bit turns the ref2 power on. 0: ref2 power off (default). 1: ref2 power on. 1 ref1 power-on when automatic reference switchov er is disabled, this bit turns the ref1 power on. 0: ref1 power off (default). 1: ref1 power on. 0 differential reference selects the pll reference mode, differential or single-end ed. single-ended must be selected for the automatic switchover or ref1 and ref2 to work. 0: single-ended reference mode (default). 1: differential reference mode. 0x01d 4 pll status disables the pll status register readback. register disable 0: pll status register enable (default). 1: pll status register disable. 3 ld pin comparator enable enables the ld pin voltage comparator. this function is used with the ld pin current source lock detect mode. when in the internal (automatic) holdover mode, this function en ables the use of the voltage on the ld pin to determine if the pll was previously in a locked state (see figure 37 ). otherwise, this function ca n be used with the refmon and status pins to monitor the voltage on this pin. 0: disables ld pin comparator; internal/automatic holdov er controller treats this pin as true (high) (default). 1: enables ld pin comparator. 2 holdover enable along with bit 0, enables the holdover functi on. automatic holdover must be disabled during vco calibration. 0: holdover disabled (default). 1: holdover enabled. 1 external enables the external hold control through the sync pin. (this disables the internal holdover mode.) holdover control 0: automatic holdover mode; holdover controlled by automatic ho ldover circuit (default). 1: external holdover mode ; holdover controlled by sync pin. 0 holdover enable along with bit 2, enables the holdover functi on. automatic holdover must be disabled during vco calibration. 0: holdover disabled (default). 1: holdover enabled. 0x01f 6 vco cal finished read-only register. indicates status of the vco calibration. 0: vco calibration not finished. 1: vco calibration finished. 5 holdover active read-only register. indicates if the part is in the holdover state (see figure 37 ). this is not the same as holdover enabled. 0: not in holdover. 1: holdover state active. 4 ref2 selected read-only register. indicates which p ll reference is selected as the input to the pll. 0: ref1 selected (or differential reference if in differential mode). 1: ref2 selected. 3 vco frequency > threshold read-only register. indicates if the vco frequency is greater than the threshold (see table 15 , ref1, ref2, and vco frequency status monitor). 0: vco frequency is less than the threshold. 1: vco frequency is greater than the threshold.
ad9518-4 rev. a | page 54 of 64 reg. addr. (hex) bits name description 0x01f 2 ref2 frequency > threshold read-only register. indicates if the frequency of the signal at ref2 is greater than the threshold frequency set by register 0x1a, bit 6. 0: ref2 frequency is less than threshold frequency. 1: ref2 frequency is grea ter than threshold frequency. 1 ref1 frequency > threshold read-only register. indicates if the frequency of the sign al at ref2 is greater than the threshold frequency set by register 0x01a, bit 6. 0: ref1 frequency is less than threshold frequency. 1: ref1 frequency is grea ter than threshold frequency. 0 digital lock detect read-only register. digital lock detect. 0: pll is not locked. 1: pll is locked.
ad9518-4 rev. a | page 55 of 64 table 45. lvpecl outputs reg. addr. (hex) bits name description 0x0f0 4 out0 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out0 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out0 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation (default). on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down. off 1 1 total power-down, reference off; use only if there are no external load resistors. off 0x0f1 4 out1 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out1 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out1 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation. on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down (default). off 1 1 total power-down, reference off; use only if there are no external load resistors. off 0x0f2 4 out2 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out2 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out2 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation (default). on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down. off 1 1 total power-down, reference off; use only if there are no external load resistors. off
ad9518-4 rev. a | page 56 of 64 reg. addr. (hex) bits name description 0x0f3 4 out3 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out3 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out3 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation. on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down (default). off 1 1 total power-down, reference off; use only if there are no external load resistors. off 0x0f4 4 out4 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out4 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out4 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation (default). on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down. off 1 1 total power-down, reference off; use only if there are no external load resistors. off 0x0f5 4 out5 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] out5 lvpecl sets the lvpecl output differential voltage (v od ). differential voltage 3 2 v od (mv) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. [1:0] out5 power-down lvpecl power-down modes. 1 0 mode output 0 0 normal operation. on 0 1 partial power-down, reference on; use only if there are no external load resistors. off 1 0 partial power-down, reference on, safe lvpecl power-down (default). off 1 1 total power-down, reference off; use only if there are no external load resistors. off
ad9518-4 rev. a | page 57 of 64 table 46. lvpecl channel dividers reg. addr. (hex) bits name description 0x190 [7:4] divider 0 low cycles number of clock cycles (minus 1) of the divider input during which divider output stays low. a value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] divider 0 high cycles number of clock cycles (minus 1) of the divider input during which divider output stays high. a value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x191 7 divider 0 bypass bypasses and powers down the divider; routes in put to divider output. 0: uses divider. 1: bypasses divider (default). 6 divider 0 nosync nosync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 5 divider 0 force high forces divider output to high. this requires that nosync (bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 divider 0 start high selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 0 phase offset phase offset (default = 0x0). 0x192 1 divider 0 direct to output connects out0 and out1 to divider 0 or directly to vco or clk. 0: out0 and out1 are connected to divider 0 (default). 1: if register 0x1e1[1:0] = 10b, the vco is routed directly to out0 and out1. if register 0x1e1[1:0] = 00b, the clk is routed directly to out0 and out1. if register 0x1e1[1:0] = 01b, there is no effect. 0 divider 0 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x193 [7:4] divider 1 low cycles number of clock cycles (minus 1) of the divider input during which divider output stays low. a value of 0x0 means that the divider is low for one input clock cycle (default = 0xb). [3:0] divider 1 high cycles number of clock cycles (minus 1) of the divider input during which divider output stays high. a value of 0x0 means that the divider is high for one input clock cycle (default = 0xb). 0x194 7 divider 1 bypass bypasses and powers down the divider; routes in put to divider output. 0: uses divider (default). 1: bypasses divider. 6 divider 1 nosync nosync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 5 divider 1 force high forces divider output to high. this requires that nosync (bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 divider 1 start high selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 1 phase offset phase offset (default = 0x0). 0x195 1 divider 1 direct to output connects out2 and out3 to divider 1 or directly to vco or clk. 0: out2 and out3 are connected to divider 1 (default). 1: if register 0x1e1[1:0] = 10b, the vco is routed directly to out2 and out3. if register 0x1e1[1:0] = 00b, the clk is routed directly to out2 and out3. if register 0x1e1[1:0] = 01b, there is no effect. 0 divider 1 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction.
ad9518-4 rev. a | page 58 of 64 reg. addr. (hex) bits name description 0x196 [7:4] divider 2 low cycles number of clock cycles (minus 1) of the divider input during which divider output stays low. a value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] divider 2 high cycles number of clock cycles (minus 1) of the divider input during which divider output stays high. a value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x197 7 divider 2 bypass bypasses and powers down the divider; route in put to divider output. 0: uses divider (default). 1: bypasses divider. 6 divider 2 nosync nosync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 5 divider 2 force high forces divider output to high. this requires that nosync (bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 divider 2 start high select clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 2 phase offset phase offset (default = 0x0). 0x198 1 divider 2 direct to output connects out4 and out5 to divider 2 or directly to vco or clk. 0: out4 and out5 are connected to divider 2 (default). 1: if register 0x1e1[1:0] = 10b, the vco is routed directly to out4 and out5. if register 0x1e1[1:0] = 00b, the cl k is routed directly to out4 and out5. if register 0x1e1[1:0] = 01b, there is no effect. 0 divider 2 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. table 47. vco divider and clk input reg. addr (hex) bits name description 0x1e0 [2:0] vco divider 2 1 0 divide 0 0 0 2. 0 0 1 3. 0 1 0 4 (default). 0 1 1 5. 1 0 0 6. 1 0 1 output static. note that setting the vco divider static should occur only after vco calibration. 1 1 0 output static. note that setting the vco divider static should occur only after vco calibration. 1 1 1 output static. note that setting the vco divider static should occur only after vco calibration. 0x1e1 4 power down clock input section powers down the clock input section (including clk buffer, vco divider, and clk tree). 0: normal operation (default). 1: power-down. 3 power down vco clock interface powers down the interface block between vco and clock distribution. 0: normal operation (default). 1: power-down. 2 power down vco and clk powers down both vco and clk input. 0; normal operation (default). 1: power-down.
ad9518-4 rev. a | page 59 of 64 reg. addr (hex) bits name description 0x1e1 1 select vco or clk selects either the vco or the clk as the input to vco divider. 0: selects external clk as input to vco divider (default). 1: selects vco as input to vco divider; cannot bypass vco divider when this is selected. 0 bypass vco divider bypasses or uses the vco divider. 0: uses vco divider (default). 1: bypasses vco divider; cannot select vco as input when this is selected. table 48. system reg. addr. (hex) bits name description 0x230 2 power down sync powers down the sync function. 0: normal operation of the sync function (default). 1: powers down sync circuitry. 1 power down powers down the reference for distribution section. distribution reference 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. 0 soft sync the soft sync bit works the same as the sync pin, except that the polarity of the bit is reversed. that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a sync. 0: same as sync high (default). 1: same as sync low. table 49. update all registers reg. addr (hex) bits name description 0x232 0 update all registers this bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next sclk rising edge. this bit is self-clearing; that is, it does not have to be set back to 0. 1 (self-clearing): updates all active regist ers to the contents of the buffer registers.
ad9518-4 rev. a | page 60 of applications information considering an ideal adc of infinite resolution where the step size and quantization error can be ignored, the available snr can be expressed approximately by frequency planning using the ad9518 the ad9518 is a highly flexible pll. when choosing the pll settings and version of the ad9518, keep in mind the following guidelines. ? ? ? ? ? ? ? ? = j a tf dbsnr 2 1 log20) ( the ad9518 has the following four frequency dividers: the reference (or r) divider, the feedback (or n) divider, the vco divider, and the channel divider. when trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the vco divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 51 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 64 within the ad9518 family, lower vco frequencies generally result in slightly lower jitter. the difference in integrated jitter (from 12 khz to 20 mhz offset) for the same output frequency is usually less than 150 fs over the entire vco frequency range (1.45 ghz to 2.95 ghz) of the ad9518 family. if the desired frequency plan can be achieved with a version of the ad9518 that has a lower vco frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter. however, choosing a higher vco frequency may result in more flexibility in frequency planning. choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the pll loop bandwidth in either direction. adisimclk is a powerful pll modeling tool that can be downloaded from www.analog.com . it is very accurate in determining the optimal loop filter for a given application. using the ad9518 outputs for adc clock applications any high speed adc is extremely sensitive to the quality of its sampling clock. an adc can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. 18 snr = 20log 1 2 f a t j 16 t j = 1 0 0 f s 2 0 0 f s 4 0 0 f s 1 p s 2 p s 1 0 p s 14 12 10 8 6 06433-044 figure 51. snr and enob vs. analog input frequency for more information, see the an-756 application note, sampled systems and the effects of clock phase noise and jitter ; and the an-501 application note, aperture uncertainty and adc system performance , at www.analog.com . many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. (distributing a single-ended clock on a noisy pcb may result in coupled noise on the sample clock. differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) the ad9518 features lvpecl outputs that provide differential clock outputs, which enable clock solutions that maximize converter snr performance. the input requirements of the adc (differential or single-ended, logic level, termination) should be considered when selecting the best clocking/converter solution.
ad9518-4 rev. a | page 61 of 64 lvpecl clock distribution the lvpecl outputs of the ad9518 provide the lowest jitter clock signals available from the ad9518. the lvpecl outputs (because they are open emitter) require a dc termination to bias the output transistors. the simplified equivalent circuit in figure 42 shows the lvpecl output stage. in most applications, a lvpecl far-end thevenin termination (see figure 52 ) or y-termination (see figure 53 ) is recommended. in both cases, v s of the receiving buffer should match the vs_lvpecl. if not, ac coupling is recommended (see figure 54 ). v s_lvpecl lvpecl 50 ? 50 ? single-ended (not coupled) v s v s_drv lvpecl 127? 127 ? 83? 83? 0643 3-145 figure 52. dc-coupled 3.3 v lvpe cl far-end thevenin termination v s_lvpecl lvpecl z 0 = 50 ? v s = 3.3 v lvpecl 50? 50? 50? z 0 = 50 ? 06433-147 figure 53. dc-coupled 3.3 v lvpecl y-termination v s_lvpecl lvpecl v s 100? differential (coupled) transmission line lvpecl 100? 0.1nf 0.1nf 200? 200 ? 06433-146 figure 54. ac-coupled lvpecl with parallel transmission line lvpecl y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower lvpecl driver. this can be an important consideration when driving long trace lengths but is usually not an issue. in the case where vs_lvpecl = 2.5 v, the 50 termination resistor connected to ground in figure 53 should be changed to 19 . thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below v ol of the lvpecl driver. in this case, vs_lvpecl on the ad9518 should equal v s of the receiving buffer. although the resistor combination shown results in a dc bias point of vs_lvpecl ? 2 v, the actual common-mode voltage is vs_lvpecl ? 1.3 v because there is additional current flowing from the ad9518 lvpecl driver through the pull-down resistor. the circuit is identical when vs_lvpecl = 2.5 v, except that the pull-down resistor is 62.5 and the pull-up is 250 .
ad9518-4 rev. a | page 62 of 64 * compliant to jedec standards mo-220-vkkd-2 with exception to exposed pad dimension. 09020 outline dimensions 9-a forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 * 5.65 5.50 sq 5.35 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 exposed pad (bottom view) 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max top view 0.60 max 0.60 max pin 1 indicator 0.50 bsc pin 1 indicator 0.25 min figure 55. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-8) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-vkkd-2 080108- figure 56. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9518-4abcpz 2 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-8 ad9518-4abcpz-rl7 2 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-8 ad9518-4bcpz ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 AD9518-4BCPZ-REEL7 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ad9518-4/pcbz evaluation board ad9518-4a/pcbz 2 evaluation board 1 z = rohs compliant part. 2 recommended for use in new de signs; reference pcn 09_156.
ad9518-4 rev. a | page 63 of 64 notes
ad9518-4 rev. a | page 64 of 64 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06433-0-1/10(a)

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